e01e4c9115
The current lowering from GPU to NVVM does not correctly handle the following cases when lowering the gpu shuffle op. 1. When the active width is set to 32 (all lanes), then the current approach computes (1 << 32) -1 which results in poison values in the LLVM IR. We fix this by defining the active mask as (-1) >> (32 - width). 2. In the case of shuffle up, the computation of the third operand c has to be different from the other 3 modes due to the op definition in the ISA reference. (https://docs.nvidia.com/cuda/parallel-thread-execution/index.html) Specifically, the predicate value is computed as j >= maxLane for up and j <= maxLane for all other modes. We fix this by computing maskAndClamp as 32 - width for this mode. TEST: We modify the existing test and add more checks for the up mode. Reviewed By: ThomasRaoux Differential Revision: https://reviews.llvm.org/D118086
267 lines
12 KiB
C++
267 lines
12 KiB
C++
//===- LowerGpuOpsToNVVMOps.cpp - MLIR GPU to NVVM lowering passes --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a pass to generate NVVMIR operations for higher-level
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// GPU operations.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h"
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#include "mlir/Conversion/ArithmeticToLLVM/ArithmeticToLLVM.h"
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#include "mlir/Conversion/LLVMCommon/ConversionTarget.h"
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#include "mlir/Conversion/LLVMCommon/LoweringOptions.h"
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#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
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#include "mlir/Conversion/MemRefToLLVM/MemRefToLLVM.h"
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#include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h"
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#include "mlir/Dialect/Arithmetic/IR/Arithmetic.h"
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#include "mlir/Dialect/GPU/GPUDialect.h"
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#include "mlir/Dialect/GPU/Passes.h"
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#include "mlir/Dialect/LLVMIR/NVVMDialect.h"
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#include "mlir/Dialect/Math/IR/Math.h"
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#include "mlir/Dialect/MemRef/IR/MemRef.h"
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#include "mlir/IR/BlockAndValueMapping.h"
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#include "mlir/Transforms/DialectConversion.h"
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#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
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#include "llvm/Support/FormatVariadic.h"
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#include "../GPUCommon/GPUOpsLowering.h"
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#include "../GPUCommon/IndexIntrinsicsOpLowering.h"
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#include "../GPUCommon/OpToFuncCallLowering.h"
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#include "../PassDetail.h"
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using namespace mlir;
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namespace {
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/// Convert gpu dialect shfl mode enum to the equivalent nvvm one.
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static NVVM::ShflKind convertShflKind(gpu::ShuffleMode mode) {
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switch (mode) {
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case gpu::ShuffleMode::XOR:
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return NVVM::ShflKind::bfly;
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case gpu::ShuffleMode::UP:
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return NVVM::ShflKind::up;
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case gpu::ShuffleMode::DOWN:
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return NVVM::ShflKind::down;
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case gpu::ShuffleMode::IDX:
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return NVVM::ShflKind::idx;
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}
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llvm_unreachable("unknown shuffle mode");
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}
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struct GPUShuffleOpLowering : public ConvertOpToLLVMPattern<gpu::ShuffleOp> {
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using ConvertOpToLLVMPattern<gpu::ShuffleOp>::ConvertOpToLLVMPattern;
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/// Lowers a shuffle to the corresponding NVVM op.
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///
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/// Convert the `width` argument into an activeMask (a bitmask which specifies
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/// which threads participate in the shuffle) and a maskAndClamp (specifying
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/// the highest lane which participates in the shuffle).
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///
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/// %one = llvm.constant(1 : i32) : i32
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/// %minus_one = llvm.constant(-1 : i32) : i32
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/// %thirty_two = llvm.constant(32 : i32) : i32
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/// %num_lanes = llvm.sub %thirty_two, %width : i32
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/// %active_mask = llvm.lshr %minus_one, %num_lanes : i32
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/// %mask_and_clamp = llvm.sub %width, %one : i32
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/// %shfl = nvvm.shfl.sync.bfly %active_mask, %value, %offset,
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/// %mask_and_clamp : !llvm<"{ float, i1 }">
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/// %shfl_value = llvm.extractvalue %shfl[0 : index] :
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/// !llvm<"{ float, i1 }">
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/// %shfl_pred = llvm.extractvalue %shfl[1 : index] :
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/// !llvm<"{ float, i1 }">
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LogicalResult
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matchAndRewrite(gpu::ShuffleOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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Location loc = op->getLoc();
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auto valueTy = adaptor.value().getType();
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auto int32Type = IntegerType::get(rewriter.getContext(), 32);
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auto predTy = IntegerType::get(rewriter.getContext(), 1);
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auto resultTy = LLVM::LLVMStructType::getLiteral(rewriter.getContext(),
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{valueTy, predTy});
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Value one = rewriter.create<LLVM::ConstantOp>(
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loc, int32Type, rewriter.getI32IntegerAttr(1));
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Value minusOne = rewriter.create<LLVM::ConstantOp>(
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loc, int32Type, rewriter.getI32IntegerAttr(-1));
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Value thirtyTwo = rewriter.create<LLVM::ConstantOp>(
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loc, int32Type, rewriter.getI32IntegerAttr(32));
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Value numLeadInactiveLane = rewriter.create<LLVM::SubOp>(
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loc, int32Type, thirtyTwo, adaptor.width());
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// Bit mask of active lanes: `(-1) >> (32 - activeWidth)`.
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Value activeMask = rewriter.create<LLVM::LShrOp>(loc, int32Type, minusOne,
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numLeadInactiveLane);
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Value maskAndClamp;
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if (op.mode() == gpu::ShuffleMode::UP) {
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// Clamp lane: `32 - activeWidth`
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maskAndClamp = numLeadInactiveLane;
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} else {
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// Clamp lane: `activeWidth - 1`
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maskAndClamp =
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rewriter.create<LLVM::SubOp>(loc, int32Type, adaptor.width(), one);
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}
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auto returnValueAndIsValidAttr = rewriter.getUnitAttr();
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Value shfl = rewriter.create<NVVM::ShflOp>(
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loc, resultTy, activeMask, adaptor.value(), adaptor.offset(),
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maskAndClamp, convertShflKind(op.mode()), returnValueAndIsValidAttr);
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Value shflValue = rewriter.create<LLVM::ExtractValueOp>(
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loc, valueTy, shfl, rewriter.getIndexArrayAttr(0));
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Value isActiveSrcLane = rewriter.create<LLVM::ExtractValueOp>(
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loc, predTy, shfl, rewriter.getIndexArrayAttr(1));
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rewriter.replaceOp(op, {shflValue, isActiveSrcLane});
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return success();
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}
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};
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/// Import the GPU Ops to NVVM Patterns.
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#include "GPUToNVVM.cpp.inc"
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/// A pass that replaces all occurrences of GPU device operations with their
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/// corresponding NVVM equivalent.
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///
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/// This pass only handles device code and is not meant to be run on GPU host
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/// code.
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struct LowerGpuOpsToNVVMOpsPass
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: public ConvertGpuOpsToNVVMOpsBase<LowerGpuOpsToNVVMOpsPass> {
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LowerGpuOpsToNVVMOpsPass() = default;
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LowerGpuOpsToNVVMOpsPass(unsigned indexBitwidth) {
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this->indexBitwidth = indexBitwidth;
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}
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void runOnOperation() override {
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gpu::GPUModuleOp m = getOperation();
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/// Customize the bitwidth used for the device side index computations.
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LowerToLLVMOptions options(
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m.getContext(),
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DataLayout(cast<DataLayoutOpInterface>(m.getOperation())));
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options.emitCWrappers = true;
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if (indexBitwidth != kDeriveIndexBitwidthFromDataLayout)
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options.overrideIndexBitwidth(indexBitwidth);
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/// MemRef conversion for GPU to NVVM lowering. The GPU dialect uses memory
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/// space 5 for private memory attributions, but NVVM represents private
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/// memory allocations as local `alloca`s in the default address space. This
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/// converter drops the private memory space to support the use case above.
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LLVMTypeConverter converter(m.getContext(), options);
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converter.addConversion([&](MemRefType type) -> Optional<Type> {
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if (type.getMemorySpaceAsInt() !=
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gpu::GPUDialect::getPrivateAddressSpace())
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return llvm::None;
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return converter.convertType(MemRefType::Builder(type).setMemorySpace(0));
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});
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// Lowering for MMAMatrixType.
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converter.addConversion([&](gpu::MMAMatrixType type) -> Type {
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return convertMMAToLLVMType(type);
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});
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RewritePatternSet patterns(m.getContext());
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RewritePatternSet llvmPatterns(m.getContext());
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// Apply in-dialect lowering first. In-dialect lowering will replace ops
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// which need to be lowered further, which is not supported by a single
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// conversion pass.
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populateGpuRewritePatterns(patterns);
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(void)applyPatternsAndFoldGreedily(m, std::move(patterns));
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mlir::arith::populateArithmeticToLLVMConversionPatterns(converter,
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llvmPatterns);
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populateStdToLLVMConversionPatterns(converter, llvmPatterns);
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populateMemRefToLLVMConversionPatterns(converter, llvmPatterns);
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populateGpuToNVVMConversionPatterns(converter, llvmPatterns);
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populateGpuWMMAToNVVMConversionPatterns(converter, llvmPatterns);
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LLVMConversionTarget target(getContext());
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configureGpuToNVVMConversionLegality(target);
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if (failed(applyPartialConversion(m, target, std::move(llvmPatterns))))
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signalPassFailure();
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}
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};
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} // namespace
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void mlir::configureGpuToNVVMConversionLegality(ConversionTarget &target) {
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target.addIllegalOp<FuncOp>();
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target.addLegalDialect<::mlir::LLVM::LLVMDialect>();
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target.addLegalDialect<::mlir::NVVM::NVVMDialect>();
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target.addIllegalDialect<gpu::GPUDialect>();
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target.addIllegalOp<LLVM::CosOp, LLVM::ExpOp, LLVM::Exp2Op, LLVM::FAbsOp,
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LLVM::FCeilOp, LLVM::FFloorOp, LLVM::LogOp, LLVM::Log10Op,
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LLVM::Log2Op, LLVM::PowOp, LLVM::SinOp, LLVM::SqrtOp>();
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// TODO: Remove once we support replacing non-root ops.
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target.addLegalOp<gpu::YieldOp, gpu::GPUModuleOp, gpu::ModuleEndOp>();
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}
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void mlir::populateGpuToNVVMConversionPatterns(LLVMTypeConverter &converter,
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RewritePatternSet &patterns) {
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populateWithGenerated(patterns);
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patterns
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.add<GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, NVVM::ThreadIdXOp,
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NVVM::ThreadIdYOp, NVVM::ThreadIdZOp>,
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GPUIndexIntrinsicOpLowering<gpu::BlockDimOp, NVVM::BlockDimXOp,
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NVVM::BlockDimYOp, NVVM::BlockDimZOp>,
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GPUIndexIntrinsicOpLowering<gpu::BlockIdOp, NVVM::BlockIdXOp,
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NVVM::BlockIdYOp, NVVM::BlockIdZOp>,
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GPUIndexIntrinsicOpLowering<gpu::GridDimOp, NVVM::GridDimXOp,
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NVVM::GridDimYOp, NVVM::GridDimZOp>,
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GPUShuffleOpLowering, GPUReturnOpLowering>(converter);
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// Explicitly drop memory space when lowering private memory
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// attributions since NVVM models it as `alloca`s in the default
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// memory space and does not support `alloca`s with addrspace(5).
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patterns.add<GPUFuncOpLowering>(
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converter, /*allocaAddrSpace=*/0,
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StringAttr::get(&converter.getContext(),
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NVVM::NVVMDialect::getKernelFuncAttrName()));
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patterns.add<OpToFuncCallLowering<math::AbsOp>>(converter, "__nv_fabsf",
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"__nv_fabs");
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patterns.add<OpToFuncCallLowering<math::AtanOp>>(converter, "__nv_atanf",
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"__nv_atan");
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patterns.add<OpToFuncCallLowering<math::Atan2Op>>(converter, "__nv_atan2f",
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"__nv_atan2");
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patterns.add<OpToFuncCallLowering<math::CeilOp>>(converter, "__nv_ceilf",
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"__nv_ceil");
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patterns.add<OpToFuncCallLowering<math::CosOp>>(converter, "__nv_cosf",
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"__nv_cos");
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patterns.add<OpToFuncCallLowering<math::ExpOp>>(converter, "__nv_expf",
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"__nv_exp");
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patterns.add<OpToFuncCallLowering<math::Exp2Op>>(converter, "__nv_exp2f",
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"__nv_exp2");
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patterns.add<OpToFuncCallLowering<math::ExpM1Op>>(converter, "__nv_expm1f",
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"__nv_expm1");
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patterns.add<OpToFuncCallLowering<math::FloorOp>>(converter, "__nv_floorf",
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"__nv_floor");
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patterns.add<OpToFuncCallLowering<math::LogOp>>(converter, "__nv_logf",
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"__nv_log");
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patterns.add<OpToFuncCallLowering<math::Log1pOp>>(converter, "__nv_log1pf",
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"__nv_log1p");
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patterns.add<OpToFuncCallLowering<math::Log10Op>>(converter, "__nv_log10f",
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"__nv_log10");
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patterns.add<OpToFuncCallLowering<math::Log2Op>>(converter, "__nv_log2f",
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"__nv_log2");
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patterns.add<OpToFuncCallLowering<math::PowFOp>>(converter, "__nv_powf",
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"__nv_pow");
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patterns.add<OpToFuncCallLowering<math::RsqrtOp>>(converter, "__nv_rsqrtf",
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"__nv_rsqrt");
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patterns.add<OpToFuncCallLowering<math::SinOp>>(converter, "__nv_sinf",
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"__nv_sin");
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patterns.add<OpToFuncCallLowering<math::SqrtOp>>(converter, "__nv_sqrtf",
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"__nv_sqrt");
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patterns.add<OpToFuncCallLowering<math::TanhOp>>(converter, "__nv_tanhf",
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"__nv_tanh");
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}
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std::unique_ptr<OperationPass<gpu::GPUModuleOp>>
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mlir::createLowerGpuOpsToNVVMOpsPass(unsigned indexBitwidth) {
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return std::make_unique<LowerGpuOpsToNVVMOpsPass>(indexBitwidth);
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}
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