859c871184
This change introduces a default schedule model for the RISCV target which leaves everything unchanged except the MicroOpBufferSize. The default value of this flag in NoSched is 0. Both configurations represent in order cores (i.e. no reorder window), the difference between them comes down to whether heuristics other than latency are allowed to apply. (Implementation details below) I left the processor models which explicitly set MicroOpBufferSize=0 unchanged in this patch, but strongly suspect we should change those too. Honestly, I think the LLVM wide default for this flag should be changed, but don't have the energy to manage the updates for all targets. Implementation wise, the effect of this change is that schedule units which are ready to run *except that* one of their predecessors may not have completed yet are added to the Available list, not the Pending one. The result of this is that it becomes possible to chose to schedule a node before it's ready cycle if the heuristics prefer. This is essentially chosing to insert a resource stall instead of e.g. increasing register pressure. Note that I was initially concerned there might be a correctness aspect (as in some kind of exposed pipeline design), but the generic scheduler doesn't seem to know how to insert noop instructions. Without that, a program wouldn't be guaranteed to schedule on an exposed pipeline depending on the program and schedule model in question. The effect of this is that we sometimes prefer register pressure in codegen results. This is mostly churn (or small wins) on scalar because we have many more registers, but is of major importance on vector - particularly high LMUL - because we effectively have many fewer registers and the relative cost of spilling is much higher. This is a significant improvement on high LMUL code quality for default rva23u configurations - or any non -mcpu vector configuration for that matter. Fixes #107532
72 lines
2.3 KiB
LLVM
72 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f,+d -target-abi=ilp32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s
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define fastcc float @callee(<32 x float> %A) nounwind {
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; CHECK-LABEL: callee:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fmv.x.w a0, fa0
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; CHECK-NEXT: ret
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%B = extractelement <32 x float> %A, i32 0
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ret float %B
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}
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; With the fastcc, arguments will be passed by fa0-fa7 and ft0-ft11.
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; The rest will be pushed on the stack.
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define float @caller(<32 x float> %A) nounwind {
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; CHECK-LABEL: caller:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -64
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; CHECK-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
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; CHECK-NEXT: fmv.w.x fa0, a0
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; CHECK-NEXT: fmv.w.x fa1, a1
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; CHECK-NEXT: fmv.w.x fa2, a2
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; CHECK-NEXT: fmv.w.x fa3, a3
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; CHECK-NEXT: fmv.w.x fa4, a4
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; CHECK-NEXT: fmv.w.x fa5, a5
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; CHECK-NEXT: fmv.w.x fa6, a6
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; CHECK-NEXT: fmv.w.x fa7, a7
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; CHECK-NEXT: flw ft0, 64(sp)
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; CHECK-NEXT: flw ft1, 68(sp)
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; CHECK-NEXT: flw ft2, 72(sp)
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; CHECK-NEXT: flw ft3, 76(sp)
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; CHECK-NEXT: flw ft4, 80(sp)
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; CHECK-NEXT: flw ft5, 84(sp)
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; CHECK-NEXT: flw ft6, 88(sp)
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; CHECK-NEXT: flw ft7, 92(sp)
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; CHECK-NEXT: flw ft8, 96(sp)
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; CHECK-NEXT: flw ft9, 100(sp)
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; CHECK-NEXT: flw ft10, 104(sp)
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; CHECK-NEXT: flw ft11, 108(sp)
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; CHECK-NEXT: flw fs0, 112(sp)
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; CHECK-NEXT: flw fs1, 116(sp)
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; CHECK-NEXT: flw fs2, 120(sp)
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; CHECK-NEXT: flw fs3, 124(sp)
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; CHECK-NEXT: flw fs4, 128(sp)
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; CHECK-NEXT: flw fs5, 132(sp)
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; CHECK-NEXT: flw fs6, 136(sp)
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; CHECK-NEXT: flw fs7, 140(sp)
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; CHECK-NEXT: flw fs8, 144(sp)
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; CHECK-NEXT: flw fs9, 148(sp)
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; CHECK-NEXT: flw fs10, 152(sp)
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; CHECK-NEXT: flw fs11, 156(sp)
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; CHECK-NEXT: fsw fs8, 32(sp)
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; CHECK-NEXT: fsw fs9, 36(sp)
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; CHECK-NEXT: fsw fs10, 40(sp)
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; CHECK-NEXT: fsw fs11, 44(sp)
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; CHECK-NEXT: fsw fs4, 16(sp)
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; CHECK-NEXT: fsw fs5, 20(sp)
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; CHECK-NEXT: fsw fs6, 24(sp)
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; CHECK-NEXT: fsw fs7, 28(sp)
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; CHECK-NEXT: fsw fs0, 0(sp)
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; CHECK-NEXT: fsw fs1, 4(sp)
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; CHECK-NEXT: fsw fs2, 8(sp)
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; CHECK-NEXT: fsw fs3, 12(sp)
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; CHECK-NEXT: call callee
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; CHECK-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
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; CHECK-NEXT: addi sp, sp, 64
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; CHECK-NEXT: ret
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%C = call fastcc float @callee(<32 x float> %A)
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ret float %C
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}
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