859c871184
This change introduces a default schedule model for the RISCV target which leaves everything unchanged except the MicroOpBufferSize. The default value of this flag in NoSched is 0. Both configurations represent in order cores (i.e. no reorder window), the difference between them comes down to whether heuristics other than latency are allowed to apply. (Implementation details below) I left the processor models which explicitly set MicroOpBufferSize=0 unchanged in this patch, but strongly suspect we should change those too. Honestly, I think the LLVM wide default for this flag should be changed, but don't have the energy to manage the updates for all targets. Implementation wise, the effect of this change is that schedule units which are ready to run *except that* one of their predecessors may not have completed yet are added to the Available list, not the Pending one. The result of this is that it becomes possible to chose to schedule a node before it's ready cycle if the heuristics prefer. This is essentially chosing to insert a resource stall instead of e.g. increasing register pressure. Note that I was initially concerned there might be a correctness aspect (as in some kind of exposed pipeline design), but the generic scheduler doesn't seem to know how to insert noop instructions. Without that, a program wouldn't be guaranteed to schedule on an exposed pipeline depending on the program and schedule model in question. The effect of this is that we sometimes prefer register pressure in codegen results. This is mostly churn (or small wins) on scalar because we have many more registers, but is of major importance on vector - particularly high LMUL - because we effectively have many fewer registers and the relative cost of spilling is much higher. This is a significant improvement on high LMUL code quality for default rva23u configurations - or any non -mcpu vector configuration for that matter. Fixes #107532
327 lines
8.7 KiB
LLVM
327 lines
8.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -no-integrated-as < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs -no-integrated-as < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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@gi = external global i32
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define i32 @constraint_r(i32 %a) nounwind {
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; RV32I-LABEL: constraint_r:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, %hi(gi)
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; RV32I-NEXT: lw a1, %lo(gi)(a1)
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; RV32I-NEXT: #APP
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_r:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, %hi(gi)
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; RV64I-NEXT: lw a1, %lo(gi)(a1)
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; RV64I-NEXT: #APP
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = load i32, ptr @gi
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%2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)
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ret i32 %2
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}
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; Don't allow 'x0' for 'r'. Some instructions have a different behavior when
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; x0 is encoded.
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define i32 @constraint_r_zero(i32 %a) nounwind {
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; RV32I-LABEL: constraint_r_zero:
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; RV32I: # %bb.0:
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; RV32I-NEXT: li a0, 0
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; RV32I-NEXT: lui a1, %hi(gi)
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; RV32I-NEXT: lw a1, %lo(gi)(a1)
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; RV32I-NEXT: #APP
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_r_zero:
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; RV64I: # %bb.0:
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; RV64I-NEXT: li a0, 0
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; RV64I-NEXT: lui a1, %hi(gi)
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; RV64I-NEXT: lw a1, %lo(gi)(a1)
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; RV64I-NEXT: #APP
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = load i32, ptr @gi
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%2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 0, i32 %1)
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ret i32 %2
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}
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define i32 @constraint_cr(i32 %a) nounwind {
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; RV32I-LABEL: constraint_cr:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, %hi(gi)
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; RV32I-NEXT: lw a1, %lo(gi)(a1)
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; RV32I-NEXT: #APP
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; RV32I-NEXT: c.add a0, a0, a1
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_cr:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, %hi(gi)
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; RV64I-NEXT: lw a1, %lo(gi)(a1)
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; RV64I-NEXT: #APP
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; RV64I-NEXT: c.add a0, a0, a1
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = load i32, ptr @gi
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%2 = tail call i32 asm "c.add $0, $1, $2", "=^cr,0,^cr"(i32 %a, i32 %1)
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ret i32 %2
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}
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define i32 @constraint_i(i32 %a) nounwind {
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; RV32I-LABEL: constraint_i:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: addi a0, a0, 113
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_i:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: addi a0, a0, 113
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = load i32, ptr @gi
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%2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113)
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ret i32 %2
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}
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define void @constraint_I() nounwind {
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; RV32I-LABEL: constraint_I:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: addi a0, a0, 2047
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: #APP
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; RV32I-NEXT: addi a0, a0, -2048
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_I:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: addi a0, a0, 2047
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: #APP
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; RV64I-NEXT: addi a0, a0, -2048
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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tail call void asm sideeffect "addi a0, a0, $0", "I"(i32 2047)
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tail call void asm sideeffect "addi a0, a0, $0", "I"(i32 -2048)
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ret void
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}
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define void @constraint_J() nounwind {
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; RV32I-LABEL: constraint_J:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: addi a0, a0, 0
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_J:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: addi a0, a0, 0
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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tail call void asm sideeffect "addi a0, a0, $0", "J"(i32 0)
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ret void
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}
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define void @constraint_K() nounwind {
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; RV32I-LABEL: constraint_K:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: csrwi mstatus, 31
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: #APP
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; RV32I-NEXT: csrwi mstatus, 0
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_K:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: csrwi mstatus, 31
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: #APP
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; RV64I-NEXT: csrwi mstatus, 0
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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tail call void asm sideeffect "csrwi mstatus, $0", "K"(i32 31)
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tail call void asm sideeffect "csrwi mstatus, $0", "K"(i32 0)
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ret void
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}
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define i32 @modifier_z_zero(i32 %a) nounwind {
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; RV32I-LABEL: modifier_z_zero:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: add a0, a0, zero
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: modifier_z_zero:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: add a0, a0, zero
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,i"(i32 %a, i32 0)
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ret i32 %1
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}
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define i32 @modifier_z_nonzero(i32 %a) nounwind {
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; RV32I-LABEL: modifier_z_nonzero:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: add a0, a0, 1
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: modifier_z_nonzero:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: add a0, a0, 1
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,i"(i32 %a, i32 1)
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ret i32 %1
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}
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define i32 @modifier_i_imm(i32 %a) nounwind {
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; RV32I-LABEL: modifier_i_imm:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: addi a0, a0, 1
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: modifier_i_imm:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: addi a0, a0, 1
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = tail call i32 asm "add${2:i} $0, $1, $2", "=r,r,ri"(i32 %a, i32 1)
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ret i32 %1
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}
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define i32 @modifier_i_reg(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: modifier_i_reg:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: modifier_i_reg:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = tail call i32 asm "add${2:i} $0, $1, $2", "=r,r,ri"(i32 %a, i32 %b)
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ret i32 %1
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}
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;; `.insn 0x4, 0x33 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)` is the
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;; raw encoding of `add`
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define i32 @modifier_N_reg(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: modifier_N_reg:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: .insn 0x4, 0x33 | (10 << 7) | (10 << 15) | (11 << 20)
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: modifier_N_reg:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: .insn 0x4, 0x33 | (10 << 7) | (10 << 15) | (11 << 20)
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = tail call i32 asm ".insn 0x4, 0x33 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=r,r,r"(i32 %a, i32 %b)
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ret i32 %1
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}
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;; `.insn 0x2, 0x9422 | (${0:N} << 7) | (${2:N} << 2)` is the raw encoding of
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;; `c.add` (note the constraint that the first input should be the same as the
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;; output).
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define i32 @modifier_N_with_cr_reg(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: modifier_N_with_cr_reg:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: .insn 0x2, 0x9422 | (10 << 7) | (11 << 2)
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: modifier_N_with_cr_reg:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: .insn 0x2, 0x9422 | (10 << 7) | (11 << 2)
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = tail call i32 asm ".insn 0x2, 0x9422 | (${0:N} << 7) | (${2:N} << 2)", "=^cr,0,^cr"(i32 %a, i32 %b)
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ret i32 %1
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}
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define void @operand_global() nounwind {
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; RV32I-LABEL: operand_global:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: .8byte gi
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: operand_global:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: .8byte gi
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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tail call void asm sideeffect ".8byte $0", "i"(ptr @gi)
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ret void
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}
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define void @operand_block_address() nounwind {
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; RV32I-LABEL: operand_block_address:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: j .Ltmp0
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: .Ltmp0: # Block address taken
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; RV32I-NEXT: # %bb.1: # %bb
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: operand_block_address:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: j .Ltmp0
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: .Ltmp0: # Block address taken
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; RV64I-NEXT: # %bb.1: # %bb
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; RV64I-NEXT: ret
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call void asm sideeffect "j $0", "i"(ptr blockaddress(@operand_block_address, %bb))
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br label %bb
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bb:
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ret void
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}
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; TODO: expand tests for more complex constraints, out of range immediates etc
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