859c871184
This change introduces a default schedule model for the RISCV target which leaves everything unchanged except the MicroOpBufferSize. The default value of this flag in NoSched is 0. Both configurations represent in order cores (i.e. no reorder window), the difference between them comes down to whether heuristics other than latency are allowed to apply. (Implementation details below) I left the processor models which explicitly set MicroOpBufferSize=0 unchanged in this patch, but strongly suspect we should change those too. Honestly, I think the LLVM wide default for this flag should be changed, but don't have the energy to manage the updates for all targets. Implementation wise, the effect of this change is that schedule units which are ready to run *except that* one of their predecessors may not have completed yet are added to the Available list, not the Pending one. The result of this is that it becomes possible to chose to schedule a node before it's ready cycle if the heuristics prefer. This is essentially chosing to insert a resource stall instead of e.g. increasing register pressure. Note that I was initially concerned there might be a correctness aspect (as in some kind of exposed pipeline design), but the generic scheduler doesn't seem to know how to insert noop instructions. Without that, a program wouldn't be guaranteed to schedule on an exposed pipeline depending on the program and schedule model in question. The effect of this is that we sometimes prefer register pressure in codegen results. This is mostly churn (or small wins) on scalar because we have many more registers, but is of major importance on vector - particularly high LMUL - because we effectively have many fewer registers and the relative cost of spilling is much higher. This is a significant improvement on high LMUL code quality for default rva23u configurations - or any non -mcpu vector configuration for that matter. Fixes #107532
3574 lines
128 KiB
LLVM
3574 lines
128 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,RV64
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,RV64
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=ZVBB,ZVBB-RV32
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=ZVBB,ZVBB-RV64
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; Integers
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define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
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; CHECK-LABEL: vector_interleave_nxv32i1_nxv16i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; CHECK-NEXT: vmv1r.v v9, v0
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: vmv.v.i v10, 0
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
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; CHECK-NEXT: vmv1r.v v0, v9
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; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
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; CHECK-NEXT: srli a1, a1, 2
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; CHECK-NEXT: vwaddu.vv v16, v8, v12
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; CHECK-NEXT: vwmaccu.vx v16, a0, v12
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; CHECK-NEXT: vmsne.vi v8, v18, 0
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; CHECK-NEXT: vmsne.vi v0, v16, 0
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; CHECK-NEXT: add a0, a1, a1
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; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
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; CHECK-NEXT: vslideup.vx v0, v8, a1
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; CHECK-NEXT: ret
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;
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; ZVBB-LABEL: vector_interleave_nxv32i1_nxv16i1:
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; ZVBB: # %bb.0:
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; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, mu
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; ZVBB-NEXT: vmv1r.v v9, v0
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; ZVBB-NEXT: vmv1r.v v0, v8
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; ZVBB-NEXT: vmv.v.i v10, 0
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; ZVBB-NEXT: li a0, 1
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; ZVBB-NEXT: csrr a1, vlenb
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; ZVBB-NEXT: vmerge.vim v10, v10, 1, v0
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; ZVBB-NEXT: srli a1, a1, 2
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; ZVBB-NEXT: vwsll.vi v12, v10, 8
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; ZVBB-NEXT: vmv1r.v v0, v9
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; ZVBB-NEXT: vwaddu.wx v12, v12, a0, v0.t
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; ZVBB-NEXT: vmsne.vi v8, v14, 0
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; ZVBB-NEXT: vmsne.vi v0, v12, 0
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; ZVBB-NEXT: add a0, a1, a1
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; ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
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; ZVBB-NEXT: vslideup.vx v0, v8, a1
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; ZVBB-NEXT: ret
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%res = call <vscale x 32 x i1> @llvm.vector.interleave2.nxv32i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
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ret <vscale x 32 x i1> %res
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}
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define <vscale x 32 x i8> @vector_interleave_nxv32i8_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: vector_interleave_nxv32i8_nxv16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; CHECK-NEXT: vwaddu.vv v12, v8, v10
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v12, a0, v10
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; CHECK-NEXT: vmv4r.v v8, v12
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; CHECK-NEXT: ret
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;
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; ZVBB-LABEL: vector_interleave_nxv32i8_nxv16i8:
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; ZVBB: # %bb.0:
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; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; ZVBB-NEXT: vwsll.vi v12, v10, 8
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; ZVBB-NEXT: vwaddu.wv v12, v12, v8
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; ZVBB-NEXT: vmv4r.v v8, v12
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; ZVBB-NEXT: ret
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%res = call <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
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ret <vscale x 32 x i8> %res
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}
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define <vscale x 16 x i16> @vector_interleave_nxv16i16_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: vector_interleave_nxv16i16_nxv8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
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; CHECK-NEXT: vwaddu.vv v12, v8, v10
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v12, a0, v10
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; CHECK-NEXT: vmv4r.v v8, v12
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; CHECK-NEXT: ret
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;
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; ZVBB-LABEL: vector_interleave_nxv16i16_nxv8i16:
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; ZVBB: # %bb.0:
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; ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
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; ZVBB-NEXT: vwsll.vi v12, v10, 16
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; ZVBB-NEXT: vwaddu.wv v12, v12, v8
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; ZVBB-NEXT: vmv4r.v v8, v12
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; ZVBB-NEXT: ret
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%res = call <vscale x 16 x i16> @llvm.vector.interleave2.nxv16i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
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ret <vscale x 16 x i16> %res
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}
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define <vscale x 8 x i32> @vector_interleave_nxv8i32_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: vector_interleave_nxv8i32_nxv4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vwaddu.vv v12, v8, v10
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v12, a0, v10
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; CHECK-NEXT: vmv4r.v v8, v12
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; CHECK-NEXT: ret
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;
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; ZVBB-LABEL: vector_interleave_nxv8i32_nxv4i32:
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; ZVBB: # %bb.0:
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; ZVBB-NEXT: li a0, 32
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; ZVBB-NEXT: vsetvli a1, zero, e32, m2, ta, ma
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; ZVBB-NEXT: vwsll.vx v12, v10, a0
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; ZVBB-NEXT: vwaddu.wv v12, v12, v8
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; ZVBB-NEXT: vmv4r.v v8, v12
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; ZVBB-NEXT: ret
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%res = call <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
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ret <vscale x 8 x i32> %res
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}
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define <vscale x 4 x i64> @vector_interleave_nxv4i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: vector_interleave_nxv4i64_nxv2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
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; CHECK-NEXT: vid.v v12
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; CHECK-NEXT: srli a0, a0, 2
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; CHECK-NEXT: vsrl.vi v16, v12, 1
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; CHECK-NEXT: vand.vi v12, v12, 1
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; CHECK-NEXT: vmsne.vi v0, v12, 0
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; CHECK-NEXT: vadd.vx v16, v16, a0, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
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; CHECK-NEXT: vmv.v.v v8, v12
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; CHECK-NEXT: ret
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;
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; ZVBB-LABEL: vector_interleave_nxv4i64_nxv2i64:
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; ZVBB: # %bb.0:
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; ZVBB-NEXT: csrr a0, vlenb
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; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, mu
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; ZVBB-NEXT: vid.v v12
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; ZVBB-NEXT: srli a0, a0, 2
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; ZVBB-NEXT: vsrl.vi v16, v12, 1
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; ZVBB-NEXT: vand.vi v12, v12, 1
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; ZVBB-NEXT: vmsne.vi v0, v12, 0
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; ZVBB-NEXT: vadd.vx v16, v16, a0, v0.t
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; ZVBB-NEXT: vsetvli zero, zero, e64, m4, ta, ma
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; ZVBB-NEXT: vrgatherei16.vv v12, v8, v16
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; ZVBB-NEXT: vmv.v.v v8, v12
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; ZVBB-NEXT: ret
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%res = call <vscale x 4 x i64> @llvm.vector.interleave2.nxv4i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
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ret <vscale x 4 x i64> %res
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}
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define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b) {
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; CHECK-LABEL: vector_interleave_nxv128i1_nxv64i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
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; CHECK-NEXT: vmv1r.v v9, v0
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: vmv.v.i v24, 0
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
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; CHECK-NEXT: vmv1r.v v0, v9
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; CHECK-NEXT: vmerge.vim v24, v24, 1, v0
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; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
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; CHECK-NEXT: vwaddu.vv v8, v24, v16
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; CHECK-NEXT: vwaddu.vv v0, v28, v20
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; CHECK-NEXT: vwmaccu.vx v8, a0, v16
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; CHECK-NEXT: vwmaccu.vx v0, a0, v20
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; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
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; CHECK-NEXT: vmsne.vi v16, v8, 0
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; CHECK-NEXT: vmsne.vi v8, v0, 0
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; CHECK-NEXT: vmv1r.v v0, v16
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; CHECK-NEXT: ret
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;
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; ZVBB-LABEL: vector_interleave_nxv128i1_nxv64i1:
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; ZVBB: # %bb.0:
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; ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
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; ZVBB-NEXT: vmv.v.i v24, 0
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; ZVBB-NEXT: vmerge.vim v16, v24, 1, v0
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; ZVBB-NEXT: vmv1r.v v0, v8
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; ZVBB-NEXT: vmerge.vim v24, v24, 1, v0
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; ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
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; ZVBB-NEXT: vwsll.vi v8, v24, 8
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; ZVBB-NEXT: vwsll.vi v0, v28, 8
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; ZVBB-NEXT: vwaddu.wv v8, v8, v16
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; ZVBB-NEXT: vwaddu.wv v0, v0, v20
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; ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
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; ZVBB-NEXT: vmsne.vi v16, v8, 0
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; ZVBB-NEXT: vmsne.vi v8, v0, 0
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; ZVBB-NEXT: vmv1r.v v0, v16
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; ZVBB-NEXT: ret
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%res = call <vscale x 128 x i1> @llvm.vector.interleave2.nxv128i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b)
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ret <vscale x 128 x i1> %res
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}
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define <vscale x 128 x i8> @vector_interleave_nxv128i8_nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) {
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; CHECK-LABEL: vector_interleave_nxv128i8_nxv64i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
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; CHECK-NEXT: vmv8r.v v24, v8
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; CHECK-NEXT: vwaddu.vv v8, v24, v16
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwaddu.vv v0, v28, v20
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; CHECK-NEXT: vwmaccu.vx v8, a0, v16
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; CHECK-NEXT: vwmaccu.vx v0, a0, v20
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; CHECK-NEXT: vmv8r.v v16, v0
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; CHECK-NEXT: ret
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;
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; ZVBB-LABEL: vector_interleave_nxv128i8_nxv64i8:
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; ZVBB: # %bb.0:
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; ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
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; ZVBB-NEXT: vwsll.vi v24, v16, 8
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; ZVBB-NEXT: vwsll.vi v0, v20, 8
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; ZVBB-NEXT: vwaddu.wv v24, v24, v8
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; ZVBB-NEXT: vwaddu.wv v0, v0, v12
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; ZVBB-NEXT: vmv8r.v v8, v24
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; ZVBB-NEXT: vmv8r.v v16, v0
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; ZVBB-NEXT: ret
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%res = call <vscale x 128 x i8> @llvm.vector.interleave2.nxv128i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b)
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ret <vscale x 128 x i8> %res
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}
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define <vscale x 64 x i16> @vector_interleave_nxv64i16_nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) {
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; CHECK-LABEL: vector_interleave_nxv64i16_nxv32i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
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; CHECK-NEXT: vmv8r.v v24, v8
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; CHECK-NEXT: vwaddu.vv v8, v24, v16
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwaddu.vv v0, v28, v20
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; CHECK-NEXT: vwmaccu.vx v8, a0, v16
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; CHECK-NEXT: vwmaccu.vx v0, a0, v20
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; CHECK-NEXT: vmv8r.v v16, v0
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; CHECK-NEXT: ret
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;
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; ZVBB-LABEL: vector_interleave_nxv64i16_nxv32i16:
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; ZVBB: # %bb.0:
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; ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
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; ZVBB-NEXT: vwsll.vi v24, v16, 16
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; ZVBB-NEXT: vwsll.vi v0, v20, 16
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; ZVBB-NEXT: vwaddu.wv v24, v24, v8
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; ZVBB-NEXT: vwaddu.wv v0, v0, v12
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; ZVBB-NEXT: vmv8r.v v8, v24
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; ZVBB-NEXT: vmv8r.v v16, v0
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; ZVBB-NEXT: ret
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%res = call <vscale x 64 x i16> @llvm.vector.interleave2.nxv64i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b)
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ret <vscale x 64 x i16> %res
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}
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define <vscale x 32 x i32> @vector_interleave_nxv32i32_nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) {
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; CHECK-LABEL: vector_interleave_nxv32i32_nxv16i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv8r.v v24, v8
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; CHECK-NEXT: vwaddu.vv v8, v24, v16
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwaddu.vv v0, v28, v20
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; CHECK-NEXT: vwmaccu.vx v8, a0, v16
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; CHECK-NEXT: vwmaccu.vx v0, a0, v20
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; CHECK-NEXT: vmv8r.v v16, v0
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; CHECK-NEXT: ret
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;
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; ZVBB-LABEL: vector_interleave_nxv32i32_nxv16i32:
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; ZVBB: # %bb.0:
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; ZVBB-NEXT: li a0, 32
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; ZVBB-NEXT: vsetvli a1, zero, e32, m4, ta, ma
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; ZVBB-NEXT: vwsll.vx v24, v16, a0
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; ZVBB-NEXT: vwsll.vx v0, v20, a0
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; ZVBB-NEXT: vwaddu.wv v24, v24, v8
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; ZVBB-NEXT: vwaddu.wv v0, v0, v12
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; ZVBB-NEXT: vmv8r.v v8, v24
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; ZVBB-NEXT: vmv8r.v v16, v0
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; ZVBB-NEXT: ret
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%res = call <vscale x 32 x i32> @llvm.vector.interleave2.nxv32i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b)
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ret <vscale x 32 x i32> %res
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}
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define <vscale x 16 x i64> @vector_interleave_nxv16i64_nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) {
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; CHECK-LABEL: vector_interleave_nxv16i64_nxv8i64:
|
|
; CHECK: # %bb.0:
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|
; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
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; CHECK-NEXT: vid.v v6
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|
; CHECK-NEXT: vmv8r.v v24, v8
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; CHECK-NEXT: srli a0, a0, 1
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; CHECK-NEXT: vmv4r.v v28, v16
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; CHECK-NEXT: vmv4r.v v16, v12
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; CHECK-NEXT: vsrl.vi v4, v6, 1
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; CHECK-NEXT: vand.vi v8, v6, 1
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: vadd.vx v4, v4, a0, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vrgatherei16.vv v8, v24, v4
|
|
; CHECK-NEXT: vrgatherei16.vv v24, v16, v4
|
|
; CHECK-NEXT: vmv.v.v v16, v24
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv16i64_nxv8i64:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: vsetvli a1, zero, e16, m2, ta, mu
|
|
; ZVBB-NEXT: vid.v v6
|
|
; ZVBB-NEXT: vmv8r.v v24, v8
|
|
; ZVBB-NEXT: srli a0, a0, 1
|
|
; ZVBB-NEXT: vmv4r.v v28, v16
|
|
; ZVBB-NEXT: vmv4r.v v16, v12
|
|
; ZVBB-NEXT: vsrl.vi v4, v6, 1
|
|
; ZVBB-NEXT: vand.vi v8, v6, 1
|
|
; ZVBB-NEXT: vmsne.vi v0, v8, 0
|
|
; ZVBB-NEXT: vadd.vx v4, v4, a0, v0.t
|
|
; ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; ZVBB-NEXT: vrgatherei16.vv v8, v24, v4
|
|
; ZVBB-NEXT: vrgatherei16.vv v24, v16, v4
|
|
; ZVBB-NEXT: vmv.v.v v16, v24
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 16 x i64> @llvm.vector.interleave2.nxv16i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b)
|
|
ret <vscale x 16 x i64> %res
|
|
}
|
|
|
|
|
|
; Floats
|
|
|
|
define <vscale x 4 x bfloat> @vector_interleave_nxv4bf16_nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) {
|
|
; CHECK-LABEL: vector_interleave_nxv4bf16_nxv2bf16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vwaddu.vv v10, v8, v9
|
|
; CHECK-NEXT: li a0, -1
|
|
; CHECK-NEXT: csrr a1, vlenb
|
|
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
|
|
; CHECK-NEXT: srli a1, a1, 2
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; CHECK-NEXT: vslidedown.vx v8, v10, a1
|
|
; CHECK-NEXT: add a0, a1, a1
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
|
|
; CHECK-NEXT: vslideup.vx v10, v8, a1
|
|
; CHECK-NEXT: vmv.v.v v8, v10
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv4bf16_nxv2bf16:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
|
|
; ZVBB-NEXT: vwsll.vi v10, v9, 16
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
|
|
; ZVBB-NEXT: srli a0, a0, 2
|
|
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
|
|
; ZVBB-NEXT: vslidedown.vx v8, v10, a0
|
|
; ZVBB-NEXT: add a1, a0, a0
|
|
; ZVBB-NEXT: vsetvli zero, a1, e16, m1, ta, ma
|
|
; ZVBB-NEXT: vslideup.vx v10, v8, a0
|
|
; ZVBB-NEXT: vmv.v.v v8, v10
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 4 x bfloat> @llvm.vector.interleave2.nxv4bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b)
|
|
ret <vscale x 4 x bfloat> %res
|
|
}
|
|
|
|
define <vscale x 8 x bfloat> @vector_interleave_nxv8bf16_nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) {
|
|
; CHECK-LABEL: vector_interleave_nxv8bf16_nxv4bf16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; CHECK-NEXT: vwaddu.vv v10, v8, v9
|
|
; CHECK-NEXT: li a0, -1
|
|
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
|
|
; CHECK-NEXT: vmv2r.v v8, v10
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv8bf16_nxv4bf16:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; ZVBB-NEXT: vwsll.vi v10, v9, 16
|
|
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
|
|
; ZVBB-NEXT: vmv2r.v v8, v10
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 8 x bfloat> @llvm.vector.interleave2.nxv8bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b)
|
|
ret <vscale x 8 x bfloat> %res
|
|
}
|
|
|
|
define <vscale x 4 x half> @vector_interleave_nxv4f16_nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b) {
|
|
; CHECK-LABEL: vector_interleave_nxv4f16_nxv2f16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vwaddu.vv v10, v8, v9
|
|
; CHECK-NEXT: li a0, -1
|
|
; CHECK-NEXT: csrr a1, vlenb
|
|
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
|
|
; CHECK-NEXT: srli a1, a1, 2
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; CHECK-NEXT: vslidedown.vx v8, v10, a1
|
|
; CHECK-NEXT: add a0, a1, a1
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
|
|
; CHECK-NEXT: vslideup.vx v10, v8, a1
|
|
; CHECK-NEXT: vmv.v.v v8, v10
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv4f16_nxv2f16:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
|
|
; ZVBB-NEXT: vwsll.vi v10, v9, 16
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
|
|
; ZVBB-NEXT: srli a0, a0, 2
|
|
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
|
|
; ZVBB-NEXT: vslidedown.vx v8, v10, a0
|
|
; ZVBB-NEXT: add a1, a0, a0
|
|
; ZVBB-NEXT: vsetvli zero, a1, e16, m1, ta, ma
|
|
; ZVBB-NEXT: vslideup.vx v10, v8, a0
|
|
; ZVBB-NEXT: vmv.v.v v8, v10
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 4 x half> @llvm.vector.interleave2.nxv4f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b)
|
|
ret <vscale x 4 x half> %res
|
|
}
|
|
|
|
define <vscale x 8 x half> @vector_interleave_nxv8f16_nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {
|
|
; CHECK-LABEL: vector_interleave_nxv8f16_nxv4f16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; CHECK-NEXT: vwaddu.vv v10, v8, v9
|
|
; CHECK-NEXT: li a0, -1
|
|
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
|
|
; CHECK-NEXT: vmv2r.v v8, v10
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv8f16_nxv4f16:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; ZVBB-NEXT: vwsll.vi v10, v9, 16
|
|
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
|
|
; ZVBB-NEXT: vmv2r.v v8, v10
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 8 x half> @llvm.vector.interleave2.nxv8f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b)
|
|
ret <vscale x 8 x half> %res
|
|
}
|
|
|
|
define <vscale x 4 x float> @vector_interleave_nxv4f32_nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b) {
|
|
; CHECK-LABEL: vector_interleave_nxv4f32_nxv2f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; CHECK-NEXT: vwaddu.vv v10, v8, v9
|
|
; CHECK-NEXT: li a0, -1
|
|
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
|
|
; CHECK-NEXT: vmv2r.v v8, v10
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv4f32_nxv2f32:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: li a0, 32
|
|
; ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
|
|
; ZVBB-NEXT: vwsll.vx v10, v9, a0
|
|
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
|
|
; ZVBB-NEXT: vmv2r.v v8, v10
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 4 x float> @llvm.vector.interleave2.nxv4f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b)
|
|
ret <vscale x 4 x float> %res
|
|
}
|
|
|
|
define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
|
|
; CHECK-LABEL: vector_interleave_nxv16bf16_nxv8bf16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
|
|
; CHECK-NEXT: vwaddu.vv v12, v8, v10
|
|
; CHECK-NEXT: li a0, -1
|
|
; CHECK-NEXT: vwmaccu.vx v12, a0, v10
|
|
; CHECK-NEXT: vmv4r.v v8, v12
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv16bf16_nxv8bf16:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
|
|
; ZVBB-NEXT: vwsll.vi v12, v10, 16
|
|
; ZVBB-NEXT: vwaddu.wv v12, v12, v8
|
|
; ZVBB-NEXT: vmv4r.v v8, v12
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 16 x bfloat> @llvm.vector.interleave2.nxv16bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
|
|
ret <vscale x 16 x bfloat> %res
|
|
}
|
|
|
|
define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) {
|
|
; CHECK-LABEL: vector_interleave_nxv16f16_nxv8f16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
|
|
; CHECK-NEXT: vwaddu.vv v12, v8, v10
|
|
; CHECK-NEXT: li a0, -1
|
|
; CHECK-NEXT: vwmaccu.vx v12, a0, v10
|
|
; CHECK-NEXT: vmv4r.v v8, v12
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv16f16_nxv8f16:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
|
|
; ZVBB-NEXT: vwsll.vi v12, v10, 16
|
|
; ZVBB-NEXT: vwaddu.wv v12, v12, v8
|
|
; ZVBB-NEXT: vmv4r.v v8, v12
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 16 x half> @llvm.vector.interleave2.nxv16f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b)
|
|
ret <vscale x 16 x half> %res
|
|
}
|
|
|
|
define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
|
|
; CHECK-LABEL: vector_interleave_nxv8f32_nxv4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vwaddu.vv v12, v8, v10
|
|
; CHECK-NEXT: li a0, -1
|
|
; CHECK-NEXT: vwmaccu.vx v12, a0, v10
|
|
; CHECK-NEXT: vmv4r.v v8, v12
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv8f32_nxv4f32:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: li a0, 32
|
|
; ZVBB-NEXT: vsetvli a1, zero, e32, m2, ta, ma
|
|
; ZVBB-NEXT: vwsll.vx v12, v10, a0
|
|
; ZVBB-NEXT: vwaddu.wv v12, v12, v8
|
|
; ZVBB-NEXT: vmv4r.v v8, v12
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 8 x float> @llvm.vector.interleave2.nxv8f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b)
|
|
ret <vscale x 8 x float> %res
|
|
}
|
|
|
|
define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {
|
|
; CHECK-LABEL: vector_interleave_nxv4f64_nxv2f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
|
|
; CHECK-NEXT: vid.v v12
|
|
; CHECK-NEXT: srli a0, a0, 2
|
|
; CHECK-NEXT: vsrl.vi v16, v12, 1
|
|
; CHECK-NEXT: vand.vi v12, v12, 1
|
|
; CHECK-NEXT: vmsne.vi v0, v12, 0
|
|
; CHECK-NEXT: vadd.vx v16, v16, a0, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
|
|
; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
|
|
; CHECK-NEXT: vmv.v.v v8, v12
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv4f64_nxv2f64:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, mu
|
|
; ZVBB-NEXT: vid.v v12
|
|
; ZVBB-NEXT: srli a0, a0, 2
|
|
; ZVBB-NEXT: vsrl.vi v16, v12, 1
|
|
; ZVBB-NEXT: vand.vi v12, v12, 1
|
|
; ZVBB-NEXT: vmsne.vi v0, v12, 0
|
|
; ZVBB-NEXT: vadd.vx v16, v16, a0, v0.t
|
|
; ZVBB-NEXT: vsetvli zero, zero, e64, m4, ta, ma
|
|
; ZVBB-NEXT: vrgatherei16.vv v12, v8, v16
|
|
; ZVBB-NEXT: vmv.v.v v8, v12
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 4 x double> @llvm.vector.interleave2.nxv4f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b)
|
|
ret <vscale x 4 x double> %res
|
|
}
|
|
|
|
|
|
|
|
define <vscale x 64 x bfloat> @vector_interleave_nxv64bf16_nxv32bf16(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b) {
|
|
; CHECK-LABEL: vector_interleave_nxv64bf16_nxv32bf16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; CHECK-NEXT: vmv8r.v v24, v8
|
|
; CHECK-NEXT: vwaddu.vv v8, v24, v16
|
|
; CHECK-NEXT: li a0, -1
|
|
; CHECK-NEXT: vwaddu.vv v0, v28, v20
|
|
; CHECK-NEXT: vwmaccu.vx v8, a0, v16
|
|
; CHECK-NEXT: vwmaccu.vx v0, a0, v20
|
|
; CHECK-NEXT: vmv8r.v v16, v0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv64bf16_nxv32bf16:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; ZVBB-NEXT: vwsll.vi v24, v16, 16
|
|
; ZVBB-NEXT: vwsll.vi v0, v20, 16
|
|
; ZVBB-NEXT: vwaddu.wv v24, v24, v8
|
|
; ZVBB-NEXT: vwaddu.wv v0, v0, v12
|
|
; ZVBB-NEXT: vmv8r.v v8, v24
|
|
; ZVBB-NEXT: vmv8r.v v16, v0
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 64 x bfloat> @llvm.vector.interleave2.nxv64bf16(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b)
|
|
ret <vscale x 64 x bfloat> %res
|
|
}
|
|
|
|
define <vscale x 64 x half> @vector_interleave_nxv64f16_nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b) {
|
|
; CHECK-LABEL: vector_interleave_nxv64f16_nxv32f16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; CHECK-NEXT: vmv8r.v v24, v8
|
|
; CHECK-NEXT: vwaddu.vv v8, v24, v16
|
|
; CHECK-NEXT: li a0, -1
|
|
; CHECK-NEXT: vwaddu.vv v0, v28, v20
|
|
; CHECK-NEXT: vwmaccu.vx v8, a0, v16
|
|
; CHECK-NEXT: vwmaccu.vx v0, a0, v20
|
|
; CHECK-NEXT: vmv8r.v v16, v0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv64f16_nxv32f16:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
|
|
; ZVBB-NEXT: vwsll.vi v24, v16, 16
|
|
; ZVBB-NEXT: vwsll.vi v0, v20, 16
|
|
; ZVBB-NEXT: vwaddu.wv v24, v24, v8
|
|
; ZVBB-NEXT: vwaddu.wv v0, v0, v12
|
|
; ZVBB-NEXT: vmv8r.v v8, v24
|
|
; ZVBB-NEXT: vmv8r.v v16, v0
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 64 x half> @llvm.vector.interleave2.nxv64f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b)
|
|
ret <vscale x 64 x half> %res
|
|
}
|
|
|
|
define <vscale x 32 x float> @vector_interleave_nxv32f32_nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b) {
|
|
; CHECK-LABEL: vector_interleave_nxv32f32_nxv16f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
|
|
; CHECK-NEXT: vmv8r.v v24, v8
|
|
; CHECK-NEXT: vwaddu.vv v8, v24, v16
|
|
; CHECK-NEXT: li a0, -1
|
|
; CHECK-NEXT: vwaddu.vv v0, v28, v20
|
|
; CHECK-NEXT: vwmaccu.vx v8, a0, v16
|
|
; CHECK-NEXT: vwmaccu.vx v0, a0, v20
|
|
; CHECK-NEXT: vmv8r.v v16, v0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv32f32_nxv16f32:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: li a0, 32
|
|
; ZVBB-NEXT: vsetvli a1, zero, e32, m4, ta, ma
|
|
; ZVBB-NEXT: vwsll.vx v24, v16, a0
|
|
; ZVBB-NEXT: vwsll.vx v0, v20, a0
|
|
; ZVBB-NEXT: vwaddu.wv v24, v24, v8
|
|
; ZVBB-NEXT: vwaddu.wv v0, v0, v12
|
|
; ZVBB-NEXT: vmv8r.v v8, v24
|
|
; ZVBB-NEXT: vmv8r.v v16, v0
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 32 x float> @llvm.vector.interleave2.nxv32f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b)
|
|
ret <vscale x 32 x float> %res
|
|
}
|
|
|
|
define <vscale x 16 x double> @vector_interleave_nxv16f64_nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b) {
|
|
; CHECK-LABEL: vector_interleave_nxv16f64_nxv8f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
|
|
; CHECK-NEXT: vid.v v6
|
|
; CHECK-NEXT: vmv8r.v v24, v8
|
|
; CHECK-NEXT: srli a0, a0, 1
|
|
; CHECK-NEXT: vmv4r.v v28, v16
|
|
; CHECK-NEXT: vmv4r.v v16, v12
|
|
; CHECK-NEXT: vsrl.vi v4, v6, 1
|
|
; CHECK-NEXT: vand.vi v8, v6, 1
|
|
; CHECK-NEXT: vmsne.vi v0, v8, 0
|
|
; CHECK-NEXT: vadd.vx v4, v4, a0, v0.t
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vrgatherei16.vv v8, v24, v4
|
|
; CHECK-NEXT: vrgatherei16.vv v24, v16, v4
|
|
; CHECK-NEXT: vmv.v.v v16, v24
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv16f64_nxv8f64:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: vsetvli a1, zero, e16, m2, ta, mu
|
|
; ZVBB-NEXT: vid.v v6
|
|
; ZVBB-NEXT: vmv8r.v v24, v8
|
|
; ZVBB-NEXT: srli a0, a0, 1
|
|
; ZVBB-NEXT: vmv4r.v v28, v16
|
|
; ZVBB-NEXT: vmv4r.v v16, v12
|
|
; ZVBB-NEXT: vsrl.vi v4, v6, 1
|
|
; ZVBB-NEXT: vand.vi v8, v6, 1
|
|
; ZVBB-NEXT: vmsne.vi v0, v8, 0
|
|
; ZVBB-NEXT: vadd.vx v4, v4, a0, v0.t
|
|
; ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; ZVBB-NEXT: vrgatherei16.vv v8, v24, v4
|
|
; ZVBB-NEXT: vrgatherei16.vv v24, v16, v4
|
|
; ZVBB-NEXT: vmv.v.v v16, v24
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 16 x double> @llvm.vector.interleave2.nxv16f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b)
|
|
ret <vscale x 16 x double> %res
|
|
}
|
|
|
|
define <vscale x 8 x i32> @vector_interleave_nxv8i32_nxv4i32_poison(<vscale x 4 x i32> %a) {
|
|
; CHECK-LABEL: vector_interleave_nxv8i32_nxv4i32_poison:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
|
|
; CHECK-NEXT: vzext.vf2 v12, v8
|
|
; CHECK-NEXT: vmv.v.v v8, v12
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv8i32_nxv4i32_poison:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
|
|
; ZVBB-NEXT: vzext.vf2 v12, v8
|
|
; ZVBB-NEXT: vmv.v.v v8, v12
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> poison)
|
|
ret <vscale x 8 x i32> %res
|
|
}
|
|
|
|
define <vscale x 8 x i32> @vector_interleave_nxv8i32_nxv4i32_poison2(<vscale x 4 x i32> %a) {
|
|
; CHECK-LABEL: vector_interleave_nxv8i32_nxv4i32_poison2:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
|
|
; CHECK-NEXT: vzext.vf2 v12, v8
|
|
; CHECK-NEXT: li a0, 32
|
|
; CHECK-NEXT: vsll.vx v8, v12, a0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv8i32_nxv4i32_poison2:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: li a0, 32
|
|
; ZVBB-NEXT: vsetvli a1, zero, e32, m2, ta, ma
|
|
; ZVBB-NEXT: vwsll.vx v12, v8, a0
|
|
; ZVBB-NEXT: vmv4r.v v8, v12
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a)
|
|
ret <vscale x 8 x i32> %res
|
|
}
|
|
|
|
define <vscale x 48 x i1> @vector_interleave_nxv48i1_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c) nounwind {
|
|
; CHECK-LABEL: vector_interleave_nxv48i1_nxv16i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: addi sp, sp, -16
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: li a1, 6
|
|
; CHECK-NEXT: mul a0, a0, a1
|
|
; CHECK-NEXT: sub sp, sp, a0
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vmv1r.v v10, v0
|
|
; CHECK-NEXT: vmv1r.v v0, v8
|
|
; CHECK-NEXT: vmv.v.i v12, 0
|
|
; CHECK-NEXT: addi a0, sp, 16
|
|
; CHECK-NEXT: csrr a1, vlenb
|
|
; CHECK-NEXT: vmerge.vim v16, v12, 1, v0
|
|
; CHECK-NEXT: slli a2, a1, 1
|
|
; CHECK-NEXT: vmv1r.v v0, v10
|
|
; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
|
|
; CHECK-NEXT: add a3, a0, a2
|
|
; CHECK-NEXT: vmv1r.v v0, v9
|
|
; CHECK-NEXT: vmerge.vim v18, v12, 1, v0
|
|
; CHECK-NEXT: add a2, a3, a2
|
|
; CHECK-NEXT: vsseg3e8.v v14, (a0)
|
|
; CHECK-NEXT: vl2r.v v8, (a2)
|
|
; CHECK-NEXT: srli a2, a1, 2
|
|
; CHECK-NEXT: srli a1, a1, 1
|
|
; CHECK-NEXT: vl2r.v v10, (a3)
|
|
; CHECK-NEXT: add a3, a2, a2
|
|
; CHECK-NEXT: vl2r.v v12, (a0)
|
|
; CHECK-NEXT: vmsne.vi v14, v8, 0
|
|
; CHECK-NEXT: vmsne.vi v8, v10, 0
|
|
; CHECK-NEXT: vmsne.vi v0, v12, 0
|
|
; CHECK-NEXT: vsetvli zero, a3, e8, mf2, ta, ma
|
|
; CHECK-NEXT: vslideup.vx v0, v8, a2
|
|
; CHECK-NEXT: add a0, a1, a1
|
|
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
|
|
; CHECK-NEXT: vslideup.vx v0, v14, a1
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: li a1, 6
|
|
; CHECK-NEXT: mul a0, a0, a1
|
|
; CHECK-NEXT: add sp, sp, a0
|
|
; CHECK-NEXT: addi sp, sp, 16
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv48i1_nxv16i1:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: addi sp, sp, -16
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: li a1, 6
|
|
; ZVBB-NEXT: mul a0, a0, a1
|
|
; ZVBB-NEXT: sub sp, sp, a0
|
|
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; ZVBB-NEXT: vmv1r.v v10, v0
|
|
; ZVBB-NEXT: vmv1r.v v0, v8
|
|
; ZVBB-NEXT: vmv.v.i v12, 0
|
|
; ZVBB-NEXT: addi a0, sp, 16
|
|
; ZVBB-NEXT: csrr a1, vlenb
|
|
; ZVBB-NEXT: vmerge.vim v16, v12, 1, v0
|
|
; ZVBB-NEXT: slli a2, a1, 1
|
|
; ZVBB-NEXT: vmv1r.v v0, v10
|
|
; ZVBB-NEXT: vmerge.vim v14, v12, 1, v0
|
|
; ZVBB-NEXT: add a3, a0, a2
|
|
; ZVBB-NEXT: vmv1r.v v0, v9
|
|
; ZVBB-NEXT: vmerge.vim v18, v12, 1, v0
|
|
; ZVBB-NEXT: add a2, a3, a2
|
|
; ZVBB-NEXT: vsseg3e8.v v14, (a0)
|
|
; ZVBB-NEXT: vl2r.v v8, (a2)
|
|
; ZVBB-NEXT: srli a2, a1, 2
|
|
; ZVBB-NEXT: srli a1, a1, 1
|
|
; ZVBB-NEXT: vl2r.v v10, (a3)
|
|
; ZVBB-NEXT: add a3, a2, a2
|
|
; ZVBB-NEXT: vl2r.v v12, (a0)
|
|
; ZVBB-NEXT: vmsne.vi v14, v8, 0
|
|
; ZVBB-NEXT: vmsne.vi v8, v10, 0
|
|
; ZVBB-NEXT: vmsne.vi v0, v12, 0
|
|
; ZVBB-NEXT: vsetvli zero, a3, e8, mf2, ta, ma
|
|
; ZVBB-NEXT: vslideup.vx v0, v8, a2
|
|
; ZVBB-NEXT: add a0, a1, a1
|
|
; ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma
|
|
; ZVBB-NEXT: vslideup.vx v0, v14, a1
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: li a1, 6
|
|
; ZVBB-NEXT: mul a0, a0, a1
|
|
; ZVBB-NEXT: add sp, sp, a0
|
|
; ZVBB-NEXT: addi sp, sp, 16
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 48 x i1> @llvm.vector.interleave3.nxv48i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c)
|
|
ret <vscale x 48 x i1> %res
|
|
}
|
|
|
|
|
|
define <vscale x 48 x i8> @vector_interleave_nxv48i8_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) nounwind {
|
|
; CHECK-LABEL: vector_interleave_nxv48i8_nxv16i8:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: addi sp, sp, -16
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: li a1, 6
|
|
; CHECK-NEXT: mul a0, a0, a1
|
|
; CHECK-NEXT: sub sp, sp, a0
|
|
; CHECK-NEXT: addi a0, sp, 16
|
|
; CHECK-NEXT: csrr a1, vlenb
|
|
; CHECK-NEXT: slli a1, a1, 1
|
|
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vsseg3e8.v v8, (a0)
|
|
; CHECK-NEXT: vl2r.v v8, (a0)
|
|
; CHECK-NEXT: add a0, a0, a1
|
|
; CHECK-NEXT: vl2r.v v10, (a0)
|
|
; CHECK-NEXT: add a0, a0, a1
|
|
; CHECK-NEXT: vl2r.v v12, (a0)
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: li a1, 6
|
|
; CHECK-NEXT: mul a0, a0, a1
|
|
; CHECK-NEXT: add sp, sp, a0
|
|
; CHECK-NEXT: addi sp, sp, 16
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv48i8_nxv16i8:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: addi sp, sp, -16
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: li a1, 6
|
|
; ZVBB-NEXT: mul a0, a0, a1
|
|
; ZVBB-NEXT: sub sp, sp, a0
|
|
; ZVBB-NEXT: addi a0, sp, 16
|
|
; ZVBB-NEXT: csrr a1, vlenb
|
|
; ZVBB-NEXT: slli a1, a1, 1
|
|
; ZVBB-NEXT: vsetvli a2, zero, e8, m2, ta, ma
|
|
; ZVBB-NEXT: vsseg3e8.v v8, (a0)
|
|
; ZVBB-NEXT: vl2r.v v8, (a0)
|
|
; ZVBB-NEXT: add a0, a0, a1
|
|
; ZVBB-NEXT: vl2r.v v10, (a0)
|
|
; ZVBB-NEXT: add a0, a0, a1
|
|
; ZVBB-NEXT: vl2r.v v12, (a0)
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: li a1, 6
|
|
; ZVBB-NEXT: mul a0, a0, a1
|
|
; ZVBB-NEXT: add sp, sp, a0
|
|
; ZVBB-NEXT: addi sp, sp, 16
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 48 x i8> @llvm.vector.interleave3.nxv48i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)
|
|
ret <vscale x 48 x i8> %res
|
|
}
|
|
|
|
|
|
define <vscale x 24 x i16> @vector_interleave_nxv24i16_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) nounwind {
|
|
; CHECK-LABEL: vector_interleave_nxv24i16_nxv8i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: addi sp, sp, -16
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: li a1, 6
|
|
; CHECK-NEXT: mul a0, a0, a1
|
|
; CHECK-NEXT: sub sp, sp, a0
|
|
; CHECK-NEXT: addi a0, sp, 16
|
|
; CHECK-NEXT: csrr a1, vlenb
|
|
; CHECK-NEXT: slli a1, a1, 1
|
|
; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, ma
|
|
; CHECK-NEXT: vsseg3e16.v v8, (a0)
|
|
; CHECK-NEXT: vl2re16.v v8, (a0)
|
|
; CHECK-NEXT: add a0, a0, a1
|
|
; CHECK-NEXT: vl2re16.v v10, (a0)
|
|
; CHECK-NEXT: add a0, a0, a1
|
|
; CHECK-NEXT: vl2re16.v v12, (a0)
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: li a1, 6
|
|
; CHECK-NEXT: mul a0, a0, a1
|
|
; CHECK-NEXT: add sp, sp, a0
|
|
; CHECK-NEXT: addi sp, sp, 16
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv24i16_nxv8i16:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: addi sp, sp, -16
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: li a1, 6
|
|
; ZVBB-NEXT: mul a0, a0, a1
|
|
; ZVBB-NEXT: sub sp, sp, a0
|
|
; ZVBB-NEXT: addi a0, sp, 16
|
|
; ZVBB-NEXT: csrr a1, vlenb
|
|
; ZVBB-NEXT: slli a1, a1, 1
|
|
; ZVBB-NEXT: vsetvli a2, zero, e16, m2, ta, ma
|
|
; ZVBB-NEXT: vsseg3e16.v v8, (a0)
|
|
; ZVBB-NEXT: vl2re16.v v8, (a0)
|
|
; ZVBB-NEXT: add a0, a0, a1
|
|
; ZVBB-NEXT: vl2re16.v v10, (a0)
|
|
; ZVBB-NEXT: add a0, a0, a1
|
|
; ZVBB-NEXT: vl2re16.v v12, (a0)
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: li a1, 6
|
|
; ZVBB-NEXT: mul a0, a0, a1
|
|
; ZVBB-NEXT: add sp, sp, a0
|
|
; ZVBB-NEXT: addi sp, sp, 16
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 24 x i16> @llvm.vector.interleave3.nxv24i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c)
|
|
ret <vscale x 24 x i16> %res
|
|
}
|
|
|
|
|
|
define <vscale x 12 x i32> @vector_interleave_nxv12i32_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) nounwind {
|
|
; CHECK-LABEL: vector_interleave_nxv12i32_nxv4i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: addi sp, sp, -16
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: li a1, 6
|
|
; CHECK-NEXT: mul a0, a0, a1
|
|
; CHECK-NEXT: sub sp, sp, a0
|
|
; CHECK-NEXT: addi a0, sp, 16
|
|
; CHECK-NEXT: csrr a1, vlenb
|
|
; CHECK-NEXT: slli a1, a1, 1
|
|
; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vsseg3e32.v v8, (a0)
|
|
; CHECK-NEXT: vl2re32.v v8, (a0)
|
|
; CHECK-NEXT: add a0, a0, a1
|
|
; CHECK-NEXT: vl2re32.v v10, (a0)
|
|
; CHECK-NEXT: add a0, a0, a1
|
|
; CHECK-NEXT: vl2re32.v v12, (a0)
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: li a1, 6
|
|
; CHECK-NEXT: mul a0, a0, a1
|
|
; CHECK-NEXT: add sp, sp, a0
|
|
; CHECK-NEXT: addi sp, sp, 16
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv12i32_nxv4i32:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: addi sp, sp, -16
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: li a1, 6
|
|
; ZVBB-NEXT: mul a0, a0, a1
|
|
; ZVBB-NEXT: sub sp, sp, a0
|
|
; ZVBB-NEXT: addi a0, sp, 16
|
|
; ZVBB-NEXT: csrr a1, vlenb
|
|
; ZVBB-NEXT: slli a1, a1, 1
|
|
; ZVBB-NEXT: vsetvli a2, zero, e32, m2, ta, ma
|
|
; ZVBB-NEXT: vsseg3e32.v v8, (a0)
|
|
; ZVBB-NEXT: vl2re32.v v8, (a0)
|
|
; ZVBB-NEXT: add a0, a0, a1
|
|
; ZVBB-NEXT: vl2re32.v v10, (a0)
|
|
; ZVBB-NEXT: add a0, a0, a1
|
|
; ZVBB-NEXT: vl2re32.v v12, (a0)
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: li a1, 6
|
|
; ZVBB-NEXT: mul a0, a0, a1
|
|
; ZVBB-NEXT: add sp, sp, a0
|
|
; ZVBB-NEXT: addi sp, sp, 16
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 12 x i32> @llvm.vector.interleave3.nxv12i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)
|
|
ret <vscale x 12 x i32> %res
|
|
}
|
|
|
|
|
|
define <vscale x 6 x i64> @vector_interleave_nxv6i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) nounwind {
|
|
; CHECK-LABEL: vector_interleave_nxv6i64_nxv2i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: addi sp, sp, -16
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: li a1, 6
|
|
; CHECK-NEXT: mul a0, a0, a1
|
|
; CHECK-NEXT: sub sp, sp, a0
|
|
; CHECK-NEXT: addi a0, sp, 16
|
|
; CHECK-NEXT: csrr a1, vlenb
|
|
; CHECK-NEXT: slli a1, a1, 1
|
|
; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vsseg3e64.v v8, (a0)
|
|
; CHECK-NEXT: vl2re64.v v8, (a0)
|
|
; CHECK-NEXT: add a0, a0, a1
|
|
; CHECK-NEXT: vl2re64.v v10, (a0)
|
|
; CHECK-NEXT: add a0, a0, a1
|
|
; CHECK-NEXT: vl2re64.v v12, (a0)
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: li a1, 6
|
|
; CHECK-NEXT: mul a0, a0, a1
|
|
; CHECK-NEXT: add sp, sp, a0
|
|
; CHECK-NEXT: addi sp, sp, 16
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv6i64_nxv2i64:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: addi sp, sp, -16
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: li a1, 6
|
|
; ZVBB-NEXT: mul a0, a0, a1
|
|
; ZVBB-NEXT: sub sp, sp, a0
|
|
; ZVBB-NEXT: addi a0, sp, 16
|
|
; ZVBB-NEXT: csrr a1, vlenb
|
|
; ZVBB-NEXT: slli a1, a1, 1
|
|
; ZVBB-NEXT: vsetvli a2, zero, e64, m2, ta, ma
|
|
; ZVBB-NEXT: vsseg3e64.v v8, (a0)
|
|
; ZVBB-NEXT: vl2re64.v v8, (a0)
|
|
; ZVBB-NEXT: add a0, a0, a1
|
|
; ZVBB-NEXT: vl2re64.v v10, (a0)
|
|
; ZVBB-NEXT: add a0, a0, a1
|
|
; ZVBB-NEXT: vl2re64.v v12, (a0)
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: li a1, 6
|
|
; ZVBB-NEXT: mul a0, a0, a1
|
|
; ZVBB-NEXT: add sp, sp, a0
|
|
; ZVBB-NEXT: addi sp, sp, 16
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 6 x i64> @llvm.vector.interleave3.nxv6i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)
|
|
ret <vscale x 6 x i64> %res
|
|
}
|
|
|
|
define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d, <vscale x 16 x i1> %e) nounwind {
|
|
; CHECK-LABEL: vector_interleave_nxv80i1_nxv16i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: addi sp, sp, -16
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: li a1, 10
|
|
; CHECK-NEXT: mul a0, a0, a1
|
|
; CHECK-NEXT: sub sp, sp, a0
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vmv.v.i v12, 0
|
|
; CHECK-NEXT: addi a4, sp, 16
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a1, a0, 2
|
|
; CHECK-NEXT: add a0, a1, a0
|
|
; CHECK-NEXT: add a0, sp, a0
|
|
; CHECK-NEXT: addi a0, a0, 16
|
|
; CHECK-NEXT: csrr a1, vlenb
|
|
; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
|
|
; CHECK-NEXT: vmv1r.v v0, v8
|
|
; CHECK-NEXT: vmerge.vim v18, v12, 1, v0
|
|
; CHECK-NEXT: add a2, a4, a1
|
|
; CHECK-NEXT: srli a3, a1, 2
|
|
; CHECK-NEXT: vmv2r.v v20, v14
|
|
; CHECK-NEXT: vmv1r.v v0, v9
|
|
; CHECK-NEXT: vmerge.vim v16, v12, 1, v0
|
|
; CHECK-NEXT: add a5, a2, a1
|
|
; CHECK-NEXT: vmv1r.v v21, v18
|
|
; CHECK-NEXT: vmv1r.v v0, v10
|
|
; CHECK-NEXT: vmerge.vim v8, v12, 1, v0
|
|
; CHECK-NEXT: vmv1r.v v22, v16
|
|
; CHECK-NEXT: vmv1r.v v16, v19
|
|
; CHECK-NEXT: vmv1r.v v23, v8
|
|
; CHECK-NEXT: vmv1r.v v18, v9
|
|
; CHECK-NEXT: vmv1r.v v0, v11
|
|
; CHECK-NEXT: vmerge.vim v24, v12, 1, v0
|
|
; CHECK-NEXT: vsetvli a6, zero, e8, m1, ta, ma
|
|
; CHECK-NEXT: vsseg5e8.v v20, (a4)
|
|
; CHECK-NEXT: vmv1r.v v19, v25
|
|
; CHECK-NEXT: vsseg5e8.v v15, (a0)
|
|
; CHECK-NEXT: vl1r.v v8, (a5)
|
|
; CHECK-NEXT: add a5, a5, a1
|
|
; CHECK-NEXT: vl1r.v v10, (a4)
|
|
; CHECK-NEXT: add a4, a5, a1
|
|
; CHECK-NEXT: vl1r.v v12, (a4)
|
|
; CHECK-NEXT: add a4, a0, a1
|
|
; CHECK-NEXT: vl1r.v v14, (a4)
|
|
; CHECK-NEXT: add a4, a4, a1
|
|
; CHECK-NEXT: vl1r.v v9, (a5)
|
|
; CHECK-NEXT: add a5, a4, a1
|
|
; CHECK-NEXT: vl1r.v v16, (a5)
|
|
; CHECK-NEXT: add a5, a5, a1
|
|
; CHECK-NEXT: srli a1, a1, 1
|
|
; CHECK-NEXT: vl1r.v v11, (a2)
|
|
; CHECK-NEXT: add a2, a3, a3
|
|
; CHECK-NEXT: vl1r.v v15, (a4)
|
|
; CHECK-NEXT: add a4, a1, a1
|
|
; CHECK-NEXT: vl1r.v v13, (a0)
|
|
; CHECK-NEXT: vl1r.v v17, (a5)
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vmsne.vi v18, v8, 0
|
|
; CHECK-NEXT: vmsne.vi v0, v10, 0
|
|
; CHECK-NEXT: vmsne.vi v8, v14, 0
|
|
; CHECK-NEXT: vmsne.vi v9, v12, 0
|
|
; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, ma
|
|
; CHECK-NEXT: vslideup.vx v0, v18, a3
|
|
; CHECK-NEXT: vslideup.vx v9, v8, a3
|
|
; CHECK-NEXT: vsetvli zero, a4, e8, m1, ta, ma
|
|
; CHECK-NEXT: vslideup.vx v0, v9, a1
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vmsne.vi v8, v16, 0
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: li a1, 10
|
|
; CHECK-NEXT: mul a0, a0, a1
|
|
; CHECK-NEXT: add sp, sp, a0
|
|
; CHECK-NEXT: addi sp, sp, 16
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv80i1_nxv16i1:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: addi sp, sp, -16
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: li a1, 10
|
|
; ZVBB-NEXT: mul a0, a0, a1
|
|
; ZVBB-NEXT: sub sp, sp, a0
|
|
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; ZVBB-NEXT: vmv.v.i v12, 0
|
|
; ZVBB-NEXT: addi a4, sp, 16
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: slli a1, a0, 2
|
|
; ZVBB-NEXT: add a0, a1, a0
|
|
; ZVBB-NEXT: add a0, sp, a0
|
|
; ZVBB-NEXT: addi a0, a0, 16
|
|
; ZVBB-NEXT: csrr a1, vlenb
|
|
; ZVBB-NEXT: vmerge.vim v14, v12, 1, v0
|
|
; ZVBB-NEXT: vmv1r.v v0, v8
|
|
; ZVBB-NEXT: vmerge.vim v18, v12, 1, v0
|
|
; ZVBB-NEXT: add a2, a4, a1
|
|
; ZVBB-NEXT: srli a3, a1, 2
|
|
; ZVBB-NEXT: vmv2r.v v20, v14
|
|
; ZVBB-NEXT: vmv1r.v v0, v9
|
|
; ZVBB-NEXT: vmerge.vim v16, v12, 1, v0
|
|
; ZVBB-NEXT: add a5, a2, a1
|
|
; ZVBB-NEXT: vmv1r.v v21, v18
|
|
; ZVBB-NEXT: vmv1r.v v0, v10
|
|
; ZVBB-NEXT: vmerge.vim v8, v12, 1, v0
|
|
; ZVBB-NEXT: vmv1r.v v22, v16
|
|
; ZVBB-NEXT: vmv1r.v v16, v19
|
|
; ZVBB-NEXT: vmv1r.v v23, v8
|
|
; ZVBB-NEXT: vmv1r.v v18, v9
|
|
; ZVBB-NEXT: vmv1r.v v0, v11
|
|
; ZVBB-NEXT: vmerge.vim v24, v12, 1, v0
|
|
; ZVBB-NEXT: vsetvli a6, zero, e8, m1, ta, ma
|
|
; ZVBB-NEXT: vsseg5e8.v v20, (a4)
|
|
; ZVBB-NEXT: vmv1r.v v19, v25
|
|
; ZVBB-NEXT: vsseg5e8.v v15, (a0)
|
|
; ZVBB-NEXT: vl1r.v v8, (a5)
|
|
; ZVBB-NEXT: add a5, a5, a1
|
|
; ZVBB-NEXT: vl1r.v v10, (a4)
|
|
; ZVBB-NEXT: add a4, a5, a1
|
|
; ZVBB-NEXT: vl1r.v v12, (a4)
|
|
; ZVBB-NEXT: add a4, a0, a1
|
|
; ZVBB-NEXT: vl1r.v v14, (a4)
|
|
; ZVBB-NEXT: add a4, a4, a1
|
|
; ZVBB-NEXT: vl1r.v v9, (a5)
|
|
; ZVBB-NEXT: add a5, a4, a1
|
|
; ZVBB-NEXT: vl1r.v v16, (a5)
|
|
; ZVBB-NEXT: add a5, a5, a1
|
|
; ZVBB-NEXT: srli a1, a1, 1
|
|
; ZVBB-NEXT: vl1r.v v11, (a2)
|
|
; ZVBB-NEXT: add a2, a3, a3
|
|
; ZVBB-NEXT: vl1r.v v15, (a4)
|
|
; ZVBB-NEXT: add a4, a1, a1
|
|
; ZVBB-NEXT: vl1r.v v13, (a0)
|
|
; ZVBB-NEXT: vl1r.v v17, (a5)
|
|
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; ZVBB-NEXT: vmsne.vi v18, v8, 0
|
|
; ZVBB-NEXT: vmsne.vi v0, v10, 0
|
|
; ZVBB-NEXT: vmsne.vi v8, v14, 0
|
|
; ZVBB-NEXT: vmsne.vi v9, v12, 0
|
|
; ZVBB-NEXT: vsetvli zero, a2, e8, mf2, ta, ma
|
|
; ZVBB-NEXT: vslideup.vx v0, v18, a3
|
|
; ZVBB-NEXT: vslideup.vx v9, v8, a3
|
|
; ZVBB-NEXT: vsetvli zero, a4, e8, m1, ta, ma
|
|
; ZVBB-NEXT: vslideup.vx v0, v9, a1
|
|
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; ZVBB-NEXT: vmsne.vi v8, v16, 0
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: li a1, 10
|
|
; ZVBB-NEXT: mul a0, a0, a1
|
|
; ZVBB-NEXT: add sp, sp, a0
|
|
; ZVBB-NEXT: addi sp, sp, 16
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 80 x i1> @llvm.vector.interleave5.nxv80i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d, <vscale x 16 x i1> %e)
|
|
ret <vscale x 80 x i1> %res
|
|
}
|
|
|
|
|
|
define <vscale x 80 x i8> @vector_interleave_nxv80i8_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e) nounwind {
|
|
;
|
|
; RV32-LABEL: vector_interleave_nxv80i8_nxv16i8:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi sp, sp, -80
|
|
; RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: addi s0, sp, 80
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: li a1, 28
|
|
; RV32-NEXT: mul a0, a0, a1
|
|
; RV32-NEXT: sub sp, sp, a0
|
|
; RV32-NEXT: andi sp, sp, -64
|
|
; RV32-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; RV32-NEXT: vmv2r.v v20, v16
|
|
; RV32-NEXT: vmv2r.v v18, v12
|
|
; RV32-NEXT: vmv2r.v v16, v8
|
|
; RV32-NEXT: addi a0, sp, 64
|
|
; RV32-NEXT: csrr a1, vlenb
|
|
; RV32-NEXT: slli a2, a1, 2
|
|
; RV32-NEXT: add a1, a2, a1
|
|
; RV32-NEXT: add a1, sp, a1
|
|
; RV32-NEXT: addi a1, a1, 64
|
|
; RV32-NEXT: csrr a2, vlenb
|
|
; RV32-NEXT: add a3, a0, a2
|
|
; RV32-NEXT: add a4, a1, a2
|
|
; RV32-NEXT: vmv2r.v v22, v16
|
|
; RV32-NEXT: vmv2r.v v24, v18
|
|
; RV32-NEXT: vmv1r.v v26, v20
|
|
; RV32-NEXT: add a5, a4, a2
|
|
; RV32-NEXT: vmv1r.v v23, v10
|
|
; RV32-NEXT: add a6, a5, a2
|
|
; RV32-NEXT: vmv1r.v v25, v14
|
|
; RV32-NEXT: vsseg5e8.v v22, (a0)
|
|
; RV32-NEXT: vmv1r.v v18, v11
|
|
; RV32-NEXT: vmv1r.v v20, v15
|
|
; RV32-NEXT: vsseg5e8.v v17, (a1)
|
|
; RV32-NEXT: vl1r.v v16, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1r.v v17, (a6)
|
|
; RV32-NEXT: add a6, a3, a2
|
|
; RV32-NEXT: vl1r.v v10, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1r.v v11, (a6)
|
|
; RV32-NEXT: vl1r.v v8, (a0)
|
|
; RV32-NEXT: vl1r.v v9, (a3)
|
|
; RV32-NEXT: vl1r.v v14, (a4)
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: li a3, 10
|
|
; RV32-NEXT: mul a0, a0, a3
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 64
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: slli a2, a2, 3
|
|
; RV32-NEXT: vl1r.v v15, (a5)
|
|
; RV32-NEXT: vl1r.v v12, (a6)
|
|
; RV32-NEXT: vl1r.v v13, (a1)
|
|
; RV32-NEXT: add a2, a0, a2
|
|
; RV32-NEXT: vs2r.v v16, (a2)
|
|
; RV32-NEXT: vs8r.v v8, (a0)
|
|
; RV32-NEXT: vl8r.v v16, (a2)
|
|
; RV32-NEXT: vl8r.v v8, (a0)
|
|
; RV32-NEXT: addi sp, s0, -80
|
|
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: addi sp, sp, 80
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vector_interleave_nxv80i8_nxv16i8:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: addi sp, sp, -80
|
|
; RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
|
|
; RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
|
|
; RV64-NEXT: addi s0, sp, 80
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: li a1, 28
|
|
; RV64-NEXT: mul a0, a0, a1
|
|
; RV64-NEXT: sub sp, sp, a0
|
|
; RV64-NEXT: andi sp, sp, -64
|
|
; RV64-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; RV64-NEXT: vmv2r.v v20, v16
|
|
; RV64-NEXT: vmv2r.v v18, v12
|
|
; RV64-NEXT: vmv2r.v v16, v8
|
|
; RV64-NEXT: addi a0, sp, 64
|
|
; RV64-NEXT: csrr a1, vlenb
|
|
; RV64-NEXT: slli a2, a1, 2
|
|
; RV64-NEXT: add a1, a2, a1
|
|
; RV64-NEXT: add a1, sp, a1
|
|
; RV64-NEXT: addi a1, a1, 64
|
|
; RV64-NEXT: csrr a2, vlenb
|
|
; RV64-NEXT: add a3, a0, a2
|
|
; RV64-NEXT: add a4, a1, a2
|
|
; RV64-NEXT: vmv2r.v v22, v16
|
|
; RV64-NEXT: vmv2r.v v24, v18
|
|
; RV64-NEXT: vmv1r.v v26, v20
|
|
; RV64-NEXT: add a5, a4, a2
|
|
; RV64-NEXT: vmv1r.v v23, v10
|
|
; RV64-NEXT: add a6, a5, a2
|
|
; RV64-NEXT: vmv1r.v v25, v14
|
|
; RV64-NEXT: vsseg5e8.v v22, (a0)
|
|
; RV64-NEXT: vmv1r.v v18, v11
|
|
; RV64-NEXT: vmv1r.v v20, v15
|
|
; RV64-NEXT: vsseg5e8.v v17, (a1)
|
|
; RV64-NEXT: vl1r.v v16, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1r.v v17, (a6)
|
|
; RV64-NEXT: add a6, a3, a2
|
|
; RV64-NEXT: vl1r.v v10, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1r.v v11, (a6)
|
|
; RV64-NEXT: vl1r.v v8, (a0)
|
|
; RV64-NEXT: vl1r.v v9, (a3)
|
|
; RV64-NEXT: vl1r.v v14, (a4)
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: li a3, 10
|
|
; RV64-NEXT: mul a0, a0, a3
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 64
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: slli a2, a2, 3
|
|
; RV64-NEXT: vl1r.v v15, (a5)
|
|
; RV64-NEXT: vl1r.v v12, (a6)
|
|
; RV64-NEXT: vl1r.v v13, (a1)
|
|
; RV64-NEXT: add a2, a0, a2
|
|
; RV64-NEXT: vs2r.v v16, (a2)
|
|
; RV64-NEXT: vs8r.v v8, (a0)
|
|
; RV64-NEXT: vl8r.v v16, (a2)
|
|
; RV64-NEXT: vl8r.v v8, (a0)
|
|
; RV64-NEXT: addi sp, s0, -80
|
|
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
|
|
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
|
|
; RV64-NEXT: addi sp, sp, 80
|
|
; RV64-NEXT: ret
|
|
;
|
|
; ZVBB-RV32-LABEL: vector_interleave_nxv80i8_nxv16i8:
|
|
; ZVBB-RV32: # %bb.0:
|
|
; ZVBB-RV32-NEXT: addi sp, sp, -80
|
|
; ZVBB-RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
|
|
; ZVBB-RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
|
|
; ZVBB-RV32-NEXT: addi s0, sp, 80
|
|
; ZVBB-RV32-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV32-NEXT: li a1, 28
|
|
; ZVBB-RV32-NEXT: mul a0, a0, a1
|
|
; ZVBB-RV32-NEXT: sub sp, sp, a0
|
|
; ZVBB-RV32-NEXT: andi sp, sp, -64
|
|
; ZVBB-RV32-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; ZVBB-RV32-NEXT: vmv2r.v v20, v16
|
|
; ZVBB-RV32-NEXT: vmv2r.v v18, v12
|
|
; ZVBB-RV32-NEXT: vmv2r.v v16, v8
|
|
; ZVBB-RV32-NEXT: addi a0, sp, 64
|
|
; ZVBB-RV32-NEXT: csrr a1, vlenb
|
|
; ZVBB-RV32-NEXT: slli a2, a1, 2
|
|
; ZVBB-RV32-NEXT: add a1, a2, a1
|
|
; ZVBB-RV32-NEXT: add a1, sp, a1
|
|
; ZVBB-RV32-NEXT: addi a1, a1, 64
|
|
; ZVBB-RV32-NEXT: csrr a2, vlenb
|
|
; ZVBB-RV32-NEXT: add a3, a0, a2
|
|
; ZVBB-RV32-NEXT: add a4, a1, a2
|
|
; ZVBB-RV32-NEXT: vmv2r.v v22, v16
|
|
; ZVBB-RV32-NEXT: vmv2r.v v24, v18
|
|
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
|
|
; ZVBB-RV32-NEXT: add a5, a4, a2
|
|
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
|
|
; ZVBB-RV32-NEXT: add a6, a5, a2
|
|
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
|
|
; ZVBB-RV32-NEXT: vsseg5e8.v v22, (a0)
|
|
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
|
|
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
|
|
; ZVBB-RV32-NEXT: vsseg5e8.v v17, (a1)
|
|
; ZVBB-RV32-NEXT: vl1r.v v16, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1r.v v17, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a3, a2
|
|
; ZVBB-RV32-NEXT: vl1r.v v10, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1r.v v11, (a6)
|
|
; ZVBB-RV32-NEXT: vl1r.v v8, (a0)
|
|
; ZVBB-RV32-NEXT: vl1r.v v9, (a3)
|
|
; ZVBB-RV32-NEXT: vl1r.v v14, (a4)
|
|
; ZVBB-RV32-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV32-NEXT: li a3, 10
|
|
; ZVBB-RV32-NEXT: mul a0, a0, a3
|
|
; ZVBB-RV32-NEXT: add a0, sp, a0
|
|
; ZVBB-RV32-NEXT: addi a0, a0, 64
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: slli a2, a2, 3
|
|
; ZVBB-RV32-NEXT: vl1r.v v15, (a5)
|
|
; ZVBB-RV32-NEXT: vl1r.v v12, (a6)
|
|
; ZVBB-RV32-NEXT: vl1r.v v13, (a1)
|
|
; ZVBB-RV32-NEXT: add a2, a0, a2
|
|
; ZVBB-RV32-NEXT: vs2r.v v16, (a2)
|
|
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
|
|
; ZVBB-RV32-NEXT: vl8r.v v16, (a2)
|
|
; ZVBB-RV32-NEXT: vl8r.v v8, (a0)
|
|
; ZVBB-RV32-NEXT: addi sp, s0, -80
|
|
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
|
|
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
|
|
; ZVBB-RV32-NEXT: addi sp, sp, 80
|
|
; ZVBB-RV32-NEXT: ret
|
|
;
|
|
; ZVBB-RV64-LABEL: vector_interleave_nxv80i8_nxv16i8:
|
|
; ZVBB-RV64: # %bb.0:
|
|
; ZVBB-RV64-NEXT: addi sp, sp, -80
|
|
; ZVBB-RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
|
|
; ZVBB-RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
|
|
; ZVBB-RV64-NEXT: addi s0, sp, 80
|
|
; ZVBB-RV64-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV64-NEXT: li a1, 28
|
|
; ZVBB-RV64-NEXT: mul a0, a0, a1
|
|
; ZVBB-RV64-NEXT: sub sp, sp, a0
|
|
; ZVBB-RV64-NEXT: andi sp, sp, -64
|
|
; ZVBB-RV64-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; ZVBB-RV64-NEXT: vmv2r.v v20, v16
|
|
; ZVBB-RV64-NEXT: vmv2r.v v18, v12
|
|
; ZVBB-RV64-NEXT: vmv2r.v v16, v8
|
|
; ZVBB-RV64-NEXT: addi a0, sp, 64
|
|
; ZVBB-RV64-NEXT: csrr a1, vlenb
|
|
; ZVBB-RV64-NEXT: slli a2, a1, 2
|
|
; ZVBB-RV64-NEXT: add a1, a2, a1
|
|
; ZVBB-RV64-NEXT: add a1, sp, a1
|
|
; ZVBB-RV64-NEXT: addi a1, a1, 64
|
|
; ZVBB-RV64-NEXT: csrr a2, vlenb
|
|
; ZVBB-RV64-NEXT: add a3, a0, a2
|
|
; ZVBB-RV64-NEXT: add a4, a1, a2
|
|
; ZVBB-RV64-NEXT: vmv2r.v v22, v16
|
|
; ZVBB-RV64-NEXT: vmv2r.v v24, v18
|
|
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
|
|
; ZVBB-RV64-NEXT: add a5, a4, a2
|
|
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
|
|
; ZVBB-RV64-NEXT: add a6, a5, a2
|
|
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
|
|
; ZVBB-RV64-NEXT: vsseg5e8.v v22, (a0)
|
|
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
|
|
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
|
|
; ZVBB-RV64-NEXT: vsseg5e8.v v17, (a1)
|
|
; ZVBB-RV64-NEXT: vl1r.v v16, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1r.v v17, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a3, a2
|
|
; ZVBB-RV64-NEXT: vl1r.v v10, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1r.v v11, (a6)
|
|
; ZVBB-RV64-NEXT: vl1r.v v8, (a0)
|
|
; ZVBB-RV64-NEXT: vl1r.v v9, (a3)
|
|
; ZVBB-RV64-NEXT: vl1r.v v14, (a4)
|
|
; ZVBB-RV64-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV64-NEXT: li a3, 10
|
|
; ZVBB-RV64-NEXT: mul a0, a0, a3
|
|
; ZVBB-RV64-NEXT: add a0, sp, a0
|
|
; ZVBB-RV64-NEXT: addi a0, a0, 64
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: slli a2, a2, 3
|
|
; ZVBB-RV64-NEXT: vl1r.v v15, (a5)
|
|
; ZVBB-RV64-NEXT: vl1r.v v12, (a6)
|
|
; ZVBB-RV64-NEXT: vl1r.v v13, (a1)
|
|
; ZVBB-RV64-NEXT: add a2, a0, a2
|
|
; ZVBB-RV64-NEXT: vs2r.v v16, (a2)
|
|
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
|
|
; ZVBB-RV64-NEXT: vl8r.v v16, (a2)
|
|
; ZVBB-RV64-NEXT: vl8r.v v8, (a0)
|
|
; ZVBB-RV64-NEXT: addi sp, s0, -80
|
|
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
|
|
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
|
|
; ZVBB-RV64-NEXT: addi sp, sp, 80
|
|
; ZVBB-RV64-NEXT: ret
|
|
%res = call <vscale x 80 x i8> @llvm.vector.interleave5.nxv80i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e)
|
|
ret <vscale x 80 x i8> %res
|
|
}
|
|
|
|
|
|
define <vscale x 40 x i8> @vector_interleave_nxv40i8_nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i8> %d, <vscale x 8 x i8> %e) nounwind {
|
|
; CHECK-LABEL: vector_interleave_nxv40i8_nxv8i8:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: addi sp, sp, -16
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a1, a0, 2
|
|
; CHECK-NEXT: add a0, a1, a0
|
|
; CHECK-NEXT: sub sp, sp, a0
|
|
; CHECK-NEXT: addi a0, sp, 16
|
|
; CHECK-NEXT: csrr a1, vlenb
|
|
; CHECK-NEXT: add a2, a0, a1
|
|
; CHECK-NEXT: add a3, a2, a1
|
|
; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
|
|
; CHECK-NEXT: vsseg5e8.v v8, (a0)
|
|
; CHECK-NEXT: vl1r.v v10, (a3)
|
|
; CHECK-NEXT: add a3, a3, a1
|
|
; CHECK-NEXT: vl1r.v v11, (a3)
|
|
; CHECK-NEXT: vl1r.v v8, (a0)
|
|
; CHECK-NEXT: vl1r.v v9, (a2)
|
|
; CHECK-NEXT: add a1, a3, a1
|
|
; CHECK-NEXT: vl1r.v v12, (a1)
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a1, a0, 2
|
|
; CHECK-NEXT: add a0, a1, a0
|
|
; CHECK-NEXT: add sp, sp, a0
|
|
; CHECK-NEXT: addi sp, sp, 16
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv40i8_nxv8i8:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: addi sp, sp, -16
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: slli a1, a0, 2
|
|
; ZVBB-NEXT: add a0, a1, a0
|
|
; ZVBB-NEXT: sub sp, sp, a0
|
|
; ZVBB-NEXT: addi a0, sp, 16
|
|
; ZVBB-NEXT: csrr a1, vlenb
|
|
; ZVBB-NEXT: add a2, a0, a1
|
|
; ZVBB-NEXT: add a3, a2, a1
|
|
; ZVBB-NEXT: vsetvli a4, zero, e8, m1, ta, ma
|
|
; ZVBB-NEXT: vsseg5e8.v v8, (a0)
|
|
; ZVBB-NEXT: vl1r.v v10, (a3)
|
|
; ZVBB-NEXT: add a3, a3, a1
|
|
; ZVBB-NEXT: vl1r.v v11, (a3)
|
|
; ZVBB-NEXT: vl1r.v v8, (a0)
|
|
; ZVBB-NEXT: vl1r.v v9, (a2)
|
|
; ZVBB-NEXT: add a1, a3, a1
|
|
; ZVBB-NEXT: vl1r.v v12, (a1)
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: slli a1, a0, 2
|
|
; ZVBB-NEXT: add a0, a1, a0
|
|
; ZVBB-NEXT: add sp, sp, a0
|
|
; ZVBB-NEXT: addi sp, sp, 16
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 40 x i8> @llvm.vector.interleave5.nxv40i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i8> %d, <vscale x 8 x i8> %e)
|
|
ret <vscale x 40 x i8> %res
|
|
}
|
|
|
|
|
|
define <vscale x 20 x i32> @vector_interleave_nxv20i32_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e) nounwind {
|
|
;
|
|
; RV32-LABEL: vector_interleave_nxv20i32_nxv4i32:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi sp, sp, -80
|
|
; RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: addi s0, sp, 80
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: li a1, 28
|
|
; RV32-NEXT: mul a0, a0, a1
|
|
; RV32-NEXT: sub sp, sp, a0
|
|
; RV32-NEXT: andi sp, sp, -64
|
|
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; RV32-NEXT: vmv2r.v v20, v16
|
|
; RV32-NEXT: vmv2r.v v18, v12
|
|
; RV32-NEXT: vmv2r.v v16, v8
|
|
; RV32-NEXT: addi a0, sp, 64
|
|
; RV32-NEXT: csrr a1, vlenb
|
|
; RV32-NEXT: slli a2, a1, 2
|
|
; RV32-NEXT: add a1, a2, a1
|
|
; RV32-NEXT: add a1, sp, a1
|
|
; RV32-NEXT: addi a1, a1, 64
|
|
; RV32-NEXT: csrr a2, vlenb
|
|
; RV32-NEXT: add a3, a0, a2
|
|
; RV32-NEXT: add a4, a1, a2
|
|
; RV32-NEXT: vmv2r.v v22, v16
|
|
; RV32-NEXT: vmv2r.v v24, v18
|
|
; RV32-NEXT: vmv1r.v v26, v20
|
|
; RV32-NEXT: add a5, a4, a2
|
|
; RV32-NEXT: vmv1r.v v23, v10
|
|
; RV32-NEXT: add a6, a5, a2
|
|
; RV32-NEXT: vmv1r.v v25, v14
|
|
; RV32-NEXT: vsseg5e32.v v22, (a0)
|
|
; RV32-NEXT: vmv1r.v v18, v11
|
|
; RV32-NEXT: vmv1r.v v20, v15
|
|
; RV32-NEXT: vsseg5e32.v v17, (a1)
|
|
; RV32-NEXT: vl1re32.v v16, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re32.v v17, (a6)
|
|
; RV32-NEXT: add a6, a3, a2
|
|
; RV32-NEXT: vl1re32.v v10, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re32.v v11, (a6)
|
|
; RV32-NEXT: vl1re32.v v8, (a0)
|
|
; RV32-NEXT: vl1re32.v v9, (a3)
|
|
; RV32-NEXT: vl1re32.v v14, (a4)
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: li a3, 10
|
|
; RV32-NEXT: mul a0, a0, a3
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 64
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: slli a2, a2, 3
|
|
; RV32-NEXT: vl1re32.v v15, (a5)
|
|
; RV32-NEXT: vl1re32.v v12, (a6)
|
|
; RV32-NEXT: vl1re32.v v13, (a1)
|
|
; RV32-NEXT: add a2, a0, a2
|
|
; RV32-NEXT: vs2r.v v16, (a2)
|
|
; RV32-NEXT: vs8r.v v8, (a0)
|
|
; RV32-NEXT: vl8re32.v v16, (a2)
|
|
; RV32-NEXT: vl8re32.v v8, (a0)
|
|
; RV32-NEXT: addi sp, s0, -80
|
|
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: addi sp, sp, 80
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vector_interleave_nxv20i32_nxv4i32:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: addi sp, sp, -80
|
|
; RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
|
|
; RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
|
|
; RV64-NEXT: addi s0, sp, 80
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: li a1, 28
|
|
; RV64-NEXT: mul a0, a0, a1
|
|
; RV64-NEXT: sub sp, sp, a0
|
|
; RV64-NEXT: andi sp, sp, -64
|
|
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; RV64-NEXT: vmv2r.v v20, v16
|
|
; RV64-NEXT: vmv2r.v v18, v12
|
|
; RV64-NEXT: vmv2r.v v16, v8
|
|
; RV64-NEXT: addi a0, sp, 64
|
|
; RV64-NEXT: csrr a1, vlenb
|
|
; RV64-NEXT: slli a2, a1, 2
|
|
; RV64-NEXT: add a1, a2, a1
|
|
; RV64-NEXT: add a1, sp, a1
|
|
; RV64-NEXT: addi a1, a1, 64
|
|
; RV64-NEXT: csrr a2, vlenb
|
|
; RV64-NEXT: add a3, a0, a2
|
|
; RV64-NEXT: add a4, a1, a2
|
|
; RV64-NEXT: vmv2r.v v22, v16
|
|
; RV64-NEXT: vmv2r.v v24, v18
|
|
; RV64-NEXT: vmv1r.v v26, v20
|
|
; RV64-NEXT: add a5, a4, a2
|
|
; RV64-NEXT: vmv1r.v v23, v10
|
|
; RV64-NEXT: add a6, a5, a2
|
|
; RV64-NEXT: vmv1r.v v25, v14
|
|
; RV64-NEXT: vsseg5e32.v v22, (a0)
|
|
; RV64-NEXT: vmv1r.v v18, v11
|
|
; RV64-NEXT: vmv1r.v v20, v15
|
|
; RV64-NEXT: vsseg5e32.v v17, (a1)
|
|
; RV64-NEXT: vl1re32.v v16, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re32.v v17, (a6)
|
|
; RV64-NEXT: add a6, a3, a2
|
|
; RV64-NEXT: vl1re32.v v10, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re32.v v11, (a6)
|
|
; RV64-NEXT: vl1re32.v v8, (a0)
|
|
; RV64-NEXT: vl1re32.v v9, (a3)
|
|
; RV64-NEXT: vl1re32.v v14, (a4)
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: li a3, 10
|
|
; RV64-NEXT: mul a0, a0, a3
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 64
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: slli a2, a2, 3
|
|
; RV64-NEXT: vl1re32.v v15, (a5)
|
|
; RV64-NEXT: vl1re32.v v12, (a6)
|
|
; RV64-NEXT: vl1re32.v v13, (a1)
|
|
; RV64-NEXT: add a2, a0, a2
|
|
; RV64-NEXT: vs2r.v v16, (a2)
|
|
; RV64-NEXT: vs8r.v v8, (a0)
|
|
; RV64-NEXT: vl8re32.v v16, (a2)
|
|
; RV64-NEXT: vl8re32.v v8, (a0)
|
|
; RV64-NEXT: addi sp, s0, -80
|
|
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
|
|
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
|
|
; RV64-NEXT: addi sp, sp, 80
|
|
; RV64-NEXT: ret
|
|
;
|
|
; ZVBB-RV32-LABEL: vector_interleave_nxv20i32_nxv4i32:
|
|
; ZVBB-RV32: # %bb.0:
|
|
; ZVBB-RV32-NEXT: addi sp, sp, -80
|
|
; ZVBB-RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
|
|
; ZVBB-RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
|
|
; ZVBB-RV32-NEXT: addi s0, sp, 80
|
|
; ZVBB-RV32-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV32-NEXT: li a1, 28
|
|
; ZVBB-RV32-NEXT: mul a0, a0, a1
|
|
; ZVBB-RV32-NEXT: sub sp, sp, a0
|
|
; ZVBB-RV32-NEXT: andi sp, sp, -64
|
|
; ZVBB-RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; ZVBB-RV32-NEXT: vmv2r.v v20, v16
|
|
; ZVBB-RV32-NEXT: vmv2r.v v18, v12
|
|
; ZVBB-RV32-NEXT: vmv2r.v v16, v8
|
|
; ZVBB-RV32-NEXT: addi a0, sp, 64
|
|
; ZVBB-RV32-NEXT: csrr a1, vlenb
|
|
; ZVBB-RV32-NEXT: slli a2, a1, 2
|
|
; ZVBB-RV32-NEXT: add a1, a2, a1
|
|
; ZVBB-RV32-NEXT: add a1, sp, a1
|
|
; ZVBB-RV32-NEXT: addi a1, a1, 64
|
|
; ZVBB-RV32-NEXT: csrr a2, vlenb
|
|
; ZVBB-RV32-NEXT: add a3, a0, a2
|
|
; ZVBB-RV32-NEXT: add a4, a1, a2
|
|
; ZVBB-RV32-NEXT: vmv2r.v v22, v16
|
|
; ZVBB-RV32-NEXT: vmv2r.v v24, v18
|
|
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
|
|
; ZVBB-RV32-NEXT: add a5, a4, a2
|
|
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
|
|
; ZVBB-RV32-NEXT: add a6, a5, a2
|
|
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
|
|
; ZVBB-RV32-NEXT: vsseg5e32.v v22, (a0)
|
|
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
|
|
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
|
|
; ZVBB-RV32-NEXT: vsseg5e32.v v17, (a1)
|
|
; ZVBB-RV32-NEXT: vl1re32.v v16, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re32.v v17, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a3, a2
|
|
; ZVBB-RV32-NEXT: vl1re32.v v10, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re32.v v11, (a6)
|
|
; ZVBB-RV32-NEXT: vl1re32.v v8, (a0)
|
|
; ZVBB-RV32-NEXT: vl1re32.v v9, (a3)
|
|
; ZVBB-RV32-NEXT: vl1re32.v v14, (a4)
|
|
; ZVBB-RV32-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV32-NEXT: li a3, 10
|
|
; ZVBB-RV32-NEXT: mul a0, a0, a3
|
|
; ZVBB-RV32-NEXT: add a0, sp, a0
|
|
; ZVBB-RV32-NEXT: addi a0, a0, 64
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: slli a2, a2, 3
|
|
; ZVBB-RV32-NEXT: vl1re32.v v15, (a5)
|
|
; ZVBB-RV32-NEXT: vl1re32.v v12, (a6)
|
|
; ZVBB-RV32-NEXT: vl1re32.v v13, (a1)
|
|
; ZVBB-RV32-NEXT: add a2, a0, a2
|
|
; ZVBB-RV32-NEXT: vs2r.v v16, (a2)
|
|
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
|
|
; ZVBB-RV32-NEXT: vl8re32.v v16, (a2)
|
|
; ZVBB-RV32-NEXT: vl8re32.v v8, (a0)
|
|
; ZVBB-RV32-NEXT: addi sp, s0, -80
|
|
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
|
|
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
|
|
; ZVBB-RV32-NEXT: addi sp, sp, 80
|
|
; ZVBB-RV32-NEXT: ret
|
|
;
|
|
; ZVBB-RV64-LABEL: vector_interleave_nxv20i32_nxv4i32:
|
|
; ZVBB-RV64: # %bb.0:
|
|
; ZVBB-RV64-NEXT: addi sp, sp, -80
|
|
; ZVBB-RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
|
|
; ZVBB-RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
|
|
; ZVBB-RV64-NEXT: addi s0, sp, 80
|
|
; ZVBB-RV64-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV64-NEXT: li a1, 28
|
|
; ZVBB-RV64-NEXT: mul a0, a0, a1
|
|
; ZVBB-RV64-NEXT: sub sp, sp, a0
|
|
; ZVBB-RV64-NEXT: andi sp, sp, -64
|
|
; ZVBB-RV64-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; ZVBB-RV64-NEXT: vmv2r.v v20, v16
|
|
; ZVBB-RV64-NEXT: vmv2r.v v18, v12
|
|
; ZVBB-RV64-NEXT: vmv2r.v v16, v8
|
|
; ZVBB-RV64-NEXT: addi a0, sp, 64
|
|
; ZVBB-RV64-NEXT: csrr a1, vlenb
|
|
; ZVBB-RV64-NEXT: slli a2, a1, 2
|
|
; ZVBB-RV64-NEXT: add a1, a2, a1
|
|
; ZVBB-RV64-NEXT: add a1, sp, a1
|
|
; ZVBB-RV64-NEXT: addi a1, a1, 64
|
|
; ZVBB-RV64-NEXT: csrr a2, vlenb
|
|
; ZVBB-RV64-NEXT: add a3, a0, a2
|
|
; ZVBB-RV64-NEXT: add a4, a1, a2
|
|
; ZVBB-RV64-NEXT: vmv2r.v v22, v16
|
|
; ZVBB-RV64-NEXT: vmv2r.v v24, v18
|
|
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
|
|
; ZVBB-RV64-NEXT: add a5, a4, a2
|
|
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
|
|
; ZVBB-RV64-NEXT: add a6, a5, a2
|
|
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
|
|
; ZVBB-RV64-NEXT: vsseg5e32.v v22, (a0)
|
|
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
|
|
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
|
|
; ZVBB-RV64-NEXT: vsseg5e32.v v17, (a1)
|
|
; ZVBB-RV64-NEXT: vl1re32.v v16, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re32.v v17, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a3, a2
|
|
; ZVBB-RV64-NEXT: vl1re32.v v10, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re32.v v11, (a6)
|
|
; ZVBB-RV64-NEXT: vl1re32.v v8, (a0)
|
|
; ZVBB-RV64-NEXT: vl1re32.v v9, (a3)
|
|
; ZVBB-RV64-NEXT: vl1re32.v v14, (a4)
|
|
; ZVBB-RV64-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV64-NEXT: li a3, 10
|
|
; ZVBB-RV64-NEXT: mul a0, a0, a3
|
|
; ZVBB-RV64-NEXT: add a0, sp, a0
|
|
; ZVBB-RV64-NEXT: addi a0, a0, 64
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: slli a2, a2, 3
|
|
; ZVBB-RV64-NEXT: vl1re32.v v15, (a5)
|
|
; ZVBB-RV64-NEXT: vl1re32.v v12, (a6)
|
|
; ZVBB-RV64-NEXT: vl1re32.v v13, (a1)
|
|
; ZVBB-RV64-NEXT: add a2, a0, a2
|
|
; ZVBB-RV64-NEXT: vs2r.v v16, (a2)
|
|
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
|
|
; ZVBB-RV64-NEXT: vl8re32.v v16, (a2)
|
|
; ZVBB-RV64-NEXT: vl8re32.v v8, (a0)
|
|
; ZVBB-RV64-NEXT: addi sp, s0, -80
|
|
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
|
|
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
|
|
; ZVBB-RV64-NEXT: addi sp, sp, 80
|
|
; ZVBB-RV64-NEXT: ret
|
|
%res = call <vscale x 20 x i32> @llvm.vector.interleave5.nxv20i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e)
|
|
ret <vscale x 20 x i32> %res
|
|
}
|
|
|
|
|
|
define <vscale x 10 x i64> @vector_interleave_nxv10i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e) nounwind {
|
|
;
|
|
; RV32-LABEL: vector_interleave_nxv10i64_nxv2i64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi sp, sp, -80
|
|
; RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: addi s0, sp, 80
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: li a1, 28
|
|
; RV32-NEXT: mul a0, a0, a1
|
|
; RV32-NEXT: sub sp, sp, a0
|
|
; RV32-NEXT: andi sp, sp, -64
|
|
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; RV32-NEXT: vmv2r.v v20, v16
|
|
; RV32-NEXT: vmv2r.v v18, v12
|
|
; RV32-NEXT: vmv2r.v v16, v8
|
|
; RV32-NEXT: addi a0, sp, 64
|
|
; RV32-NEXT: csrr a1, vlenb
|
|
; RV32-NEXT: slli a2, a1, 2
|
|
; RV32-NEXT: add a1, a2, a1
|
|
; RV32-NEXT: add a1, sp, a1
|
|
; RV32-NEXT: addi a1, a1, 64
|
|
; RV32-NEXT: csrr a2, vlenb
|
|
; RV32-NEXT: add a3, a0, a2
|
|
; RV32-NEXT: add a4, a1, a2
|
|
; RV32-NEXT: vmv2r.v v22, v16
|
|
; RV32-NEXT: vmv2r.v v24, v18
|
|
; RV32-NEXT: vmv1r.v v26, v20
|
|
; RV32-NEXT: add a5, a4, a2
|
|
; RV32-NEXT: vmv1r.v v23, v10
|
|
; RV32-NEXT: add a6, a5, a2
|
|
; RV32-NEXT: vmv1r.v v25, v14
|
|
; RV32-NEXT: vsseg5e64.v v22, (a0)
|
|
; RV32-NEXT: vmv1r.v v18, v11
|
|
; RV32-NEXT: vmv1r.v v20, v15
|
|
; RV32-NEXT: vsseg5e64.v v17, (a1)
|
|
; RV32-NEXT: vl1re64.v v16, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re64.v v17, (a6)
|
|
; RV32-NEXT: add a6, a3, a2
|
|
; RV32-NEXT: vl1re64.v v10, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re64.v v11, (a6)
|
|
; RV32-NEXT: vl1re64.v v8, (a0)
|
|
; RV32-NEXT: vl1re64.v v9, (a3)
|
|
; RV32-NEXT: vl1re64.v v14, (a4)
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: li a3, 10
|
|
; RV32-NEXT: mul a0, a0, a3
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 64
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: slli a2, a2, 3
|
|
; RV32-NEXT: vl1re64.v v15, (a5)
|
|
; RV32-NEXT: vl1re64.v v12, (a6)
|
|
; RV32-NEXT: vl1re64.v v13, (a1)
|
|
; RV32-NEXT: add a2, a0, a2
|
|
; RV32-NEXT: vs2r.v v16, (a2)
|
|
; RV32-NEXT: vs8r.v v8, (a0)
|
|
; RV32-NEXT: vl8re64.v v16, (a2)
|
|
; RV32-NEXT: vl8re64.v v8, (a0)
|
|
; RV32-NEXT: addi sp, s0, -80
|
|
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: addi sp, sp, 80
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vector_interleave_nxv10i64_nxv2i64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: addi sp, sp, -80
|
|
; RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
|
|
; RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
|
|
; RV64-NEXT: addi s0, sp, 80
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: li a1, 28
|
|
; RV64-NEXT: mul a0, a0, a1
|
|
; RV64-NEXT: sub sp, sp, a0
|
|
; RV64-NEXT: andi sp, sp, -64
|
|
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; RV64-NEXT: vmv2r.v v20, v16
|
|
; RV64-NEXT: vmv2r.v v18, v12
|
|
; RV64-NEXT: vmv2r.v v16, v8
|
|
; RV64-NEXT: addi a0, sp, 64
|
|
; RV64-NEXT: csrr a1, vlenb
|
|
; RV64-NEXT: slli a2, a1, 2
|
|
; RV64-NEXT: add a1, a2, a1
|
|
; RV64-NEXT: add a1, sp, a1
|
|
; RV64-NEXT: addi a1, a1, 64
|
|
; RV64-NEXT: csrr a2, vlenb
|
|
; RV64-NEXT: add a3, a0, a2
|
|
; RV64-NEXT: add a4, a1, a2
|
|
; RV64-NEXT: vmv2r.v v22, v16
|
|
; RV64-NEXT: vmv2r.v v24, v18
|
|
; RV64-NEXT: vmv1r.v v26, v20
|
|
; RV64-NEXT: add a5, a4, a2
|
|
; RV64-NEXT: vmv1r.v v23, v10
|
|
; RV64-NEXT: add a6, a5, a2
|
|
; RV64-NEXT: vmv1r.v v25, v14
|
|
; RV64-NEXT: vsseg5e64.v v22, (a0)
|
|
; RV64-NEXT: vmv1r.v v18, v11
|
|
; RV64-NEXT: vmv1r.v v20, v15
|
|
; RV64-NEXT: vsseg5e64.v v17, (a1)
|
|
; RV64-NEXT: vl1re64.v v16, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re64.v v17, (a6)
|
|
; RV64-NEXT: add a6, a3, a2
|
|
; RV64-NEXT: vl1re64.v v10, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re64.v v11, (a6)
|
|
; RV64-NEXT: vl1re64.v v8, (a0)
|
|
; RV64-NEXT: vl1re64.v v9, (a3)
|
|
; RV64-NEXT: vl1re64.v v14, (a4)
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: li a3, 10
|
|
; RV64-NEXT: mul a0, a0, a3
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 64
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: slli a2, a2, 3
|
|
; RV64-NEXT: vl1re64.v v15, (a5)
|
|
; RV64-NEXT: vl1re64.v v12, (a6)
|
|
; RV64-NEXT: vl1re64.v v13, (a1)
|
|
; RV64-NEXT: add a2, a0, a2
|
|
; RV64-NEXT: vs2r.v v16, (a2)
|
|
; RV64-NEXT: vs8r.v v8, (a0)
|
|
; RV64-NEXT: vl8re64.v v16, (a2)
|
|
; RV64-NEXT: vl8re64.v v8, (a0)
|
|
; RV64-NEXT: addi sp, s0, -80
|
|
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
|
|
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
|
|
; RV64-NEXT: addi sp, sp, 80
|
|
; RV64-NEXT: ret
|
|
;
|
|
; ZVBB-RV32-LABEL: vector_interleave_nxv10i64_nxv2i64:
|
|
; ZVBB-RV32: # %bb.0:
|
|
; ZVBB-RV32-NEXT: addi sp, sp, -80
|
|
; ZVBB-RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
|
|
; ZVBB-RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
|
|
; ZVBB-RV32-NEXT: addi s0, sp, 80
|
|
; ZVBB-RV32-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV32-NEXT: li a1, 28
|
|
; ZVBB-RV32-NEXT: mul a0, a0, a1
|
|
; ZVBB-RV32-NEXT: sub sp, sp, a0
|
|
; ZVBB-RV32-NEXT: andi sp, sp, -64
|
|
; ZVBB-RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; ZVBB-RV32-NEXT: vmv2r.v v20, v16
|
|
; ZVBB-RV32-NEXT: vmv2r.v v18, v12
|
|
; ZVBB-RV32-NEXT: vmv2r.v v16, v8
|
|
; ZVBB-RV32-NEXT: addi a0, sp, 64
|
|
; ZVBB-RV32-NEXT: csrr a1, vlenb
|
|
; ZVBB-RV32-NEXT: slli a2, a1, 2
|
|
; ZVBB-RV32-NEXT: add a1, a2, a1
|
|
; ZVBB-RV32-NEXT: add a1, sp, a1
|
|
; ZVBB-RV32-NEXT: addi a1, a1, 64
|
|
; ZVBB-RV32-NEXT: csrr a2, vlenb
|
|
; ZVBB-RV32-NEXT: add a3, a0, a2
|
|
; ZVBB-RV32-NEXT: add a4, a1, a2
|
|
; ZVBB-RV32-NEXT: vmv2r.v v22, v16
|
|
; ZVBB-RV32-NEXT: vmv2r.v v24, v18
|
|
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
|
|
; ZVBB-RV32-NEXT: add a5, a4, a2
|
|
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
|
|
; ZVBB-RV32-NEXT: add a6, a5, a2
|
|
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
|
|
; ZVBB-RV32-NEXT: vsseg5e64.v v22, (a0)
|
|
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
|
|
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
|
|
; ZVBB-RV32-NEXT: vsseg5e64.v v17, (a1)
|
|
; ZVBB-RV32-NEXT: vl1re64.v v16, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re64.v v17, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a3, a2
|
|
; ZVBB-RV32-NEXT: vl1re64.v v10, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re64.v v11, (a6)
|
|
; ZVBB-RV32-NEXT: vl1re64.v v8, (a0)
|
|
; ZVBB-RV32-NEXT: vl1re64.v v9, (a3)
|
|
; ZVBB-RV32-NEXT: vl1re64.v v14, (a4)
|
|
; ZVBB-RV32-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV32-NEXT: li a3, 10
|
|
; ZVBB-RV32-NEXT: mul a0, a0, a3
|
|
; ZVBB-RV32-NEXT: add a0, sp, a0
|
|
; ZVBB-RV32-NEXT: addi a0, a0, 64
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: slli a2, a2, 3
|
|
; ZVBB-RV32-NEXT: vl1re64.v v15, (a5)
|
|
; ZVBB-RV32-NEXT: vl1re64.v v12, (a6)
|
|
; ZVBB-RV32-NEXT: vl1re64.v v13, (a1)
|
|
; ZVBB-RV32-NEXT: add a2, a0, a2
|
|
; ZVBB-RV32-NEXT: vs2r.v v16, (a2)
|
|
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
|
|
; ZVBB-RV32-NEXT: vl8re64.v v16, (a2)
|
|
; ZVBB-RV32-NEXT: vl8re64.v v8, (a0)
|
|
; ZVBB-RV32-NEXT: addi sp, s0, -80
|
|
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
|
|
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
|
|
; ZVBB-RV32-NEXT: addi sp, sp, 80
|
|
; ZVBB-RV32-NEXT: ret
|
|
;
|
|
; ZVBB-RV64-LABEL: vector_interleave_nxv10i64_nxv2i64:
|
|
; ZVBB-RV64: # %bb.0:
|
|
; ZVBB-RV64-NEXT: addi sp, sp, -80
|
|
; ZVBB-RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
|
|
; ZVBB-RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
|
|
; ZVBB-RV64-NEXT: addi s0, sp, 80
|
|
; ZVBB-RV64-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV64-NEXT: li a1, 28
|
|
; ZVBB-RV64-NEXT: mul a0, a0, a1
|
|
; ZVBB-RV64-NEXT: sub sp, sp, a0
|
|
; ZVBB-RV64-NEXT: andi sp, sp, -64
|
|
; ZVBB-RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; ZVBB-RV64-NEXT: vmv2r.v v20, v16
|
|
; ZVBB-RV64-NEXT: vmv2r.v v18, v12
|
|
; ZVBB-RV64-NEXT: vmv2r.v v16, v8
|
|
; ZVBB-RV64-NEXT: addi a0, sp, 64
|
|
; ZVBB-RV64-NEXT: csrr a1, vlenb
|
|
; ZVBB-RV64-NEXT: slli a2, a1, 2
|
|
; ZVBB-RV64-NEXT: add a1, a2, a1
|
|
; ZVBB-RV64-NEXT: add a1, sp, a1
|
|
; ZVBB-RV64-NEXT: addi a1, a1, 64
|
|
; ZVBB-RV64-NEXT: csrr a2, vlenb
|
|
; ZVBB-RV64-NEXT: add a3, a0, a2
|
|
; ZVBB-RV64-NEXT: add a4, a1, a2
|
|
; ZVBB-RV64-NEXT: vmv2r.v v22, v16
|
|
; ZVBB-RV64-NEXT: vmv2r.v v24, v18
|
|
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
|
|
; ZVBB-RV64-NEXT: add a5, a4, a2
|
|
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
|
|
; ZVBB-RV64-NEXT: add a6, a5, a2
|
|
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
|
|
; ZVBB-RV64-NEXT: vsseg5e64.v v22, (a0)
|
|
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
|
|
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
|
|
; ZVBB-RV64-NEXT: vsseg5e64.v v17, (a1)
|
|
; ZVBB-RV64-NEXT: vl1re64.v v16, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re64.v v17, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a3, a2
|
|
; ZVBB-RV64-NEXT: vl1re64.v v10, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re64.v v11, (a6)
|
|
; ZVBB-RV64-NEXT: vl1re64.v v8, (a0)
|
|
; ZVBB-RV64-NEXT: vl1re64.v v9, (a3)
|
|
; ZVBB-RV64-NEXT: vl1re64.v v14, (a4)
|
|
; ZVBB-RV64-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV64-NEXT: li a3, 10
|
|
; ZVBB-RV64-NEXT: mul a0, a0, a3
|
|
; ZVBB-RV64-NEXT: add a0, sp, a0
|
|
; ZVBB-RV64-NEXT: addi a0, a0, 64
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: slli a2, a2, 3
|
|
; ZVBB-RV64-NEXT: vl1re64.v v15, (a5)
|
|
; ZVBB-RV64-NEXT: vl1re64.v v12, (a6)
|
|
; ZVBB-RV64-NEXT: vl1re64.v v13, (a1)
|
|
; ZVBB-RV64-NEXT: add a2, a0, a2
|
|
; ZVBB-RV64-NEXT: vs2r.v v16, (a2)
|
|
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
|
|
; ZVBB-RV64-NEXT: vl8re64.v v16, (a2)
|
|
; ZVBB-RV64-NEXT: vl8re64.v v8, (a0)
|
|
; ZVBB-RV64-NEXT: addi sp, s0, -80
|
|
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
|
|
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
|
|
; ZVBB-RV64-NEXT: addi sp, sp, 80
|
|
; ZVBB-RV64-NEXT: ret
|
|
%res = call <vscale x 10 x i64> @llvm.vector.interleave5.nxv10i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e)
|
|
ret <vscale x 10 x i64> %res
|
|
}
|
|
|
|
define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d, <vscale x 16 x i1> %e, <vscale x 16 x i1> %f, <vscale x 16 x i1> %g) nounwind {
|
|
; CHECK-LABEL: vector_interleave_nxv112i1_nxv16i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: addi sp, sp, -16
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: li a1, 14
|
|
; CHECK-NEXT: mul a0, a0, a1
|
|
; CHECK-NEXT: sub sp, sp, a0
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vmv.v.i v14, 0
|
|
; CHECK-NEXT: addi a4, sp, 16
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: slli a1, a0, 3
|
|
; CHECK-NEXT: sub a0, a1, a0
|
|
; CHECK-NEXT: add a0, sp, a0
|
|
; CHECK-NEXT: addi a0, a0, 16
|
|
; CHECK-NEXT: csrr a2, vlenb
|
|
; CHECK-NEXT: vmerge.vim v16, v14, 1, v0
|
|
; CHECK-NEXT: vmv1r.v v0, v8
|
|
; CHECK-NEXT: vmerge.vim v22, v14, 1, v0
|
|
; CHECK-NEXT: add a3, a4, a2
|
|
; CHECK-NEXT: srli a1, a2, 2
|
|
; CHECK-NEXT: add a5, a0, a2
|
|
; CHECK-NEXT: vmv4r.v v24, v16
|
|
; CHECK-NEXT: vmv1r.v v0, v9
|
|
; CHECK-NEXT: vmerge.vim v18, v14, 1, v0
|
|
; CHECK-NEXT: add a6, a3, a2
|
|
; CHECK-NEXT: vmv1r.v v25, v22
|
|
; CHECK-NEXT: vmv1r.v v0, v10
|
|
; CHECK-NEXT: vmerge.vim v8, v14, 1, v0
|
|
; CHECK-NEXT: add a7, a6, a2
|
|
; CHECK-NEXT: vmv1r.v v26, v18
|
|
; CHECK-NEXT: vmv1r.v v0, v11
|
|
; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
|
|
; CHECK-NEXT: vmv1r.v v27, v8
|
|
; CHECK-NEXT: vmv1r.v v0, v12
|
|
; CHECK-NEXT: vmerge.vim v10, v14, 1, v0
|
|
; CHECK-NEXT: vmv1r.v v28, v20
|
|
; CHECK-NEXT: vmv1r.v v18, v23
|
|
; CHECK-NEXT: vmv1r.v v29, v10
|
|
; CHECK-NEXT: vmv1r.v v20, v9
|
|
; CHECK-NEXT: vmv1r.v v0, v13
|
|
; CHECK-NEXT: vmerge.vim v30, v14, 1, v0
|
|
; CHECK-NEXT: vmv1r.v v22, v11
|
|
; CHECK-NEXT: vsetvli t0, zero, e8, m1, ta, ma
|
|
; CHECK-NEXT: vsseg7e8.v v24, (a4)
|
|
; CHECK-NEXT: vmv1r.v v23, v31
|
|
; CHECK-NEXT: vsseg7e8.v v17, (a0)
|
|
; CHECK-NEXT: vl1r.v v8, (a6)
|
|
; CHECK-NEXT: add a6, a7, a2
|
|
; CHECK-NEXT: vl1r.v v10, (a4)
|
|
; CHECK-NEXT: add a4, a6, a2
|
|
; CHECK-NEXT: vl1r.v v12, (a6)
|
|
; CHECK-NEXT: add a6, a4, a2
|
|
; CHECK-NEXT: vl1r.v v14, (a6)
|
|
; CHECK-NEXT: add a6, a5, a2
|
|
; CHECK-NEXT: vl1r.v v16, (a5)
|
|
; CHECK-NEXT: add a5, a6, a2
|
|
; CHECK-NEXT: vl1r.v v18, (a5)
|
|
; CHECK-NEXT: add a5, a5, a2
|
|
; CHECK-NEXT: vl1r.v v9, (a7)
|
|
; CHECK-NEXT: add a7, a5, a2
|
|
; CHECK-NEXT: vl1r.v v20, (a7)
|
|
; CHECK-NEXT: add a7, a7, a2
|
|
; CHECK-NEXT: srli a2, a2, 1
|
|
; CHECK-NEXT: vl1r.v v11, (a3)
|
|
; CHECK-NEXT: add a3, a1, a1
|
|
; CHECK-NEXT: vl1r.v v13, (a4)
|
|
; CHECK-NEXT: add a4, a2, a2
|
|
; CHECK-NEXT: vl1r.v v15, (a0)
|
|
; CHECK-NEXT: vl1r.v v19, (a5)
|
|
; CHECK-NEXT: vl1r.v v17, (a6)
|
|
; CHECK-NEXT: vl1r.v v21, (a7)
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vmsne.vi v22, v8, 0
|
|
; CHECK-NEXT: vmsne.vi v0, v10, 0
|
|
; CHECK-NEXT: vmsne.vi v9, v12, 0
|
|
; CHECK-NEXT: vmsne.vi v10, v14, 0
|
|
; CHECK-NEXT: vmsne.vi v11, v18, 0
|
|
; CHECK-NEXT: vmsne.vi v8, v16, 0
|
|
; CHECK-NEXT: vmsne.vi v12, v20, 0
|
|
; CHECK-NEXT: vsetvli zero, a3, e8, mf2, ta, ma
|
|
; CHECK-NEXT: vslideup.vx v0, v22, a1
|
|
; CHECK-NEXT: vslideup.vx v9, v10, a1
|
|
; CHECK-NEXT: vslideup.vx v8, v11, a1
|
|
; CHECK-NEXT: vsetvli zero, a4, e8, m1, ta, ma
|
|
; CHECK-NEXT: vslideup.vx v0, v9, a2
|
|
; CHECK-NEXT: vslideup.vx v8, v12, a2
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: li a1, 14
|
|
; CHECK-NEXT: mul a0, a0, a1
|
|
; CHECK-NEXT: add sp, sp, a0
|
|
; CHECK-NEXT: addi sp, sp, 16
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; ZVBB-LABEL: vector_interleave_nxv112i1_nxv16i1:
|
|
; ZVBB: # %bb.0:
|
|
; ZVBB-NEXT: addi sp, sp, -16
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: li a1, 14
|
|
; ZVBB-NEXT: mul a0, a0, a1
|
|
; ZVBB-NEXT: sub sp, sp, a0
|
|
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; ZVBB-NEXT: vmv.v.i v14, 0
|
|
; ZVBB-NEXT: addi a4, sp, 16
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: slli a1, a0, 3
|
|
; ZVBB-NEXT: sub a0, a1, a0
|
|
; ZVBB-NEXT: add a0, sp, a0
|
|
; ZVBB-NEXT: addi a0, a0, 16
|
|
; ZVBB-NEXT: csrr a2, vlenb
|
|
; ZVBB-NEXT: vmerge.vim v16, v14, 1, v0
|
|
; ZVBB-NEXT: vmv1r.v v0, v8
|
|
; ZVBB-NEXT: vmerge.vim v22, v14, 1, v0
|
|
; ZVBB-NEXT: add a3, a4, a2
|
|
; ZVBB-NEXT: srli a1, a2, 2
|
|
; ZVBB-NEXT: add a5, a0, a2
|
|
; ZVBB-NEXT: vmv4r.v v24, v16
|
|
; ZVBB-NEXT: vmv1r.v v0, v9
|
|
; ZVBB-NEXT: vmerge.vim v18, v14, 1, v0
|
|
; ZVBB-NEXT: add a6, a3, a2
|
|
; ZVBB-NEXT: vmv1r.v v25, v22
|
|
; ZVBB-NEXT: vmv1r.v v0, v10
|
|
; ZVBB-NEXT: vmerge.vim v8, v14, 1, v0
|
|
; ZVBB-NEXT: add a7, a6, a2
|
|
; ZVBB-NEXT: vmv1r.v v26, v18
|
|
; ZVBB-NEXT: vmv1r.v v0, v11
|
|
; ZVBB-NEXT: vmerge.vim v20, v14, 1, v0
|
|
; ZVBB-NEXT: vmv1r.v v27, v8
|
|
; ZVBB-NEXT: vmv1r.v v0, v12
|
|
; ZVBB-NEXT: vmerge.vim v10, v14, 1, v0
|
|
; ZVBB-NEXT: vmv1r.v v28, v20
|
|
; ZVBB-NEXT: vmv1r.v v18, v23
|
|
; ZVBB-NEXT: vmv1r.v v29, v10
|
|
; ZVBB-NEXT: vmv1r.v v20, v9
|
|
; ZVBB-NEXT: vmv1r.v v0, v13
|
|
; ZVBB-NEXT: vmerge.vim v30, v14, 1, v0
|
|
; ZVBB-NEXT: vmv1r.v v22, v11
|
|
; ZVBB-NEXT: vsetvli t0, zero, e8, m1, ta, ma
|
|
; ZVBB-NEXT: vsseg7e8.v v24, (a4)
|
|
; ZVBB-NEXT: vmv1r.v v23, v31
|
|
; ZVBB-NEXT: vsseg7e8.v v17, (a0)
|
|
; ZVBB-NEXT: vl1r.v v8, (a6)
|
|
; ZVBB-NEXT: add a6, a7, a2
|
|
; ZVBB-NEXT: vl1r.v v10, (a4)
|
|
; ZVBB-NEXT: add a4, a6, a2
|
|
; ZVBB-NEXT: vl1r.v v12, (a6)
|
|
; ZVBB-NEXT: add a6, a4, a2
|
|
; ZVBB-NEXT: vl1r.v v14, (a6)
|
|
; ZVBB-NEXT: add a6, a5, a2
|
|
; ZVBB-NEXT: vl1r.v v16, (a5)
|
|
; ZVBB-NEXT: add a5, a6, a2
|
|
; ZVBB-NEXT: vl1r.v v18, (a5)
|
|
; ZVBB-NEXT: add a5, a5, a2
|
|
; ZVBB-NEXT: vl1r.v v9, (a7)
|
|
; ZVBB-NEXT: add a7, a5, a2
|
|
; ZVBB-NEXT: vl1r.v v20, (a7)
|
|
; ZVBB-NEXT: add a7, a7, a2
|
|
; ZVBB-NEXT: srli a2, a2, 1
|
|
; ZVBB-NEXT: vl1r.v v11, (a3)
|
|
; ZVBB-NEXT: add a3, a1, a1
|
|
; ZVBB-NEXT: vl1r.v v13, (a4)
|
|
; ZVBB-NEXT: add a4, a2, a2
|
|
; ZVBB-NEXT: vl1r.v v15, (a0)
|
|
; ZVBB-NEXT: vl1r.v v19, (a5)
|
|
; ZVBB-NEXT: vl1r.v v17, (a6)
|
|
; ZVBB-NEXT: vl1r.v v21, (a7)
|
|
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; ZVBB-NEXT: vmsne.vi v22, v8, 0
|
|
; ZVBB-NEXT: vmsne.vi v0, v10, 0
|
|
; ZVBB-NEXT: vmsne.vi v9, v12, 0
|
|
; ZVBB-NEXT: vmsne.vi v10, v14, 0
|
|
; ZVBB-NEXT: vmsne.vi v11, v18, 0
|
|
; ZVBB-NEXT: vmsne.vi v8, v16, 0
|
|
; ZVBB-NEXT: vmsne.vi v12, v20, 0
|
|
; ZVBB-NEXT: vsetvli zero, a3, e8, mf2, ta, ma
|
|
; ZVBB-NEXT: vslideup.vx v0, v22, a1
|
|
; ZVBB-NEXT: vslideup.vx v9, v10, a1
|
|
; ZVBB-NEXT: vslideup.vx v8, v11, a1
|
|
; ZVBB-NEXT: vsetvli zero, a4, e8, m1, ta, ma
|
|
; ZVBB-NEXT: vslideup.vx v0, v9, a2
|
|
; ZVBB-NEXT: vslideup.vx v8, v12, a2
|
|
; ZVBB-NEXT: csrr a0, vlenb
|
|
; ZVBB-NEXT: li a1, 14
|
|
; ZVBB-NEXT: mul a0, a0, a1
|
|
; ZVBB-NEXT: add sp, sp, a0
|
|
; ZVBB-NEXT: addi sp, sp, 16
|
|
; ZVBB-NEXT: ret
|
|
%res = call <vscale x 112 x i1> @llvm.vector.interleave7.nxv112i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d, <vscale x 16 x i1> %e, <vscale x 16 x i1> %f, <vscale x 16 x i1> %g)
|
|
ret <vscale x 112 x i1> %res
|
|
}
|
|
|
|
|
|
define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e, <vscale x 16 x i8> %f, <vscale x 16 x i8> %g) nounwind {
|
|
;
|
|
; RV32-LABEL: vector_interleave_nxv112i8_nxv16i8:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi sp, sp, -80
|
|
; RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: addi s0, sp, 80
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 5
|
|
; RV32-NEXT: sub sp, sp, a0
|
|
; RV32-NEXT: andi sp, sp, -64
|
|
; RV32-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; RV32-NEXT: vmv2r.v v26, v20
|
|
; RV32-NEXT: vmv2r.v v24, v16
|
|
; RV32-NEXT: vmv2r.v v22, v12
|
|
; RV32-NEXT: vmv2r.v v20, v8
|
|
; RV32-NEXT: addi a1, sp, 64
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a2, a0, 3
|
|
; RV32-NEXT: sub a0, a2, a0
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 64
|
|
; RV32-NEXT: csrr a2, vlenb
|
|
; RV32-NEXT: add a3, a1, a2
|
|
; RV32-NEXT: add a4, a0, a2
|
|
; RV32-NEXT: slli a5, a2, 2
|
|
; RV32-NEXT: slli a6, a2, 4
|
|
; RV32-NEXT: add a7, a4, a2
|
|
; RV32-NEXT: sub a5, a6, a5
|
|
; RV32-NEXT: vmv1r.v v1, v20
|
|
; RV32-NEXT: vmv1r.v v3, v22
|
|
; RV32-NEXT: vmv1r.v v5, v24
|
|
; RV32-NEXT: vmv1r.v v7, v26
|
|
; RV32-NEXT: add a6, a7, a2
|
|
; RV32-NEXT: vmv1r.v v2, v10
|
|
; RV32-NEXT: vmv1r.v v4, v14
|
|
; RV32-NEXT: vmv1r.v v6, v18
|
|
; RV32-NEXT: vsseg7e8.v v1, (a1)
|
|
; RV32-NEXT: vmv1r.v v22, v11
|
|
; RV32-NEXT: vmv1r.v v24, v15
|
|
; RV32-NEXT: vmv1r.v v26, v19
|
|
; RV32-NEXT: vsseg7e8.v v21, (a0)
|
|
; RV32-NEXT: vl1r.v v10, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1r.v v11, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1r.v v12, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1r.v v13, (a6)
|
|
; RV32-NEXT: add a6, a3, a2
|
|
; RV32-NEXT: vl1r.v v18, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1r.v v19, (a6)
|
|
; RV32-NEXT: vl1r.v v16, (a1)
|
|
; RV32-NEXT: vl1r.v v8, (a4)
|
|
; RV32-NEXT: vl1r.v v17, (a3)
|
|
; RV32-NEXT: vl1r.v v9, (a7)
|
|
; RV32-NEXT: csrr a1, vlenb
|
|
; RV32-NEXT: li a3, 14
|
|
; RV32-NEXT: mul a1, a1, a3
|
|
; RV32-NEXT: add a1, sp, a1
|
|
; RV32-NEXT: addi a1, a1, 64
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1r.v v20, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1r.v v21, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: slli a2, a2, 3
|
|
; RV32-NEXT: add a2, a1, a2
|
|
; RV32-NEXT: add a5, a1, a5
|
|
; RV32-NEXT: vl1r.v v22, (a6)
|
|
; RV32-NEXT: vl1r.v v23, (a0)
|
|
; RV32-NEXT: vs2r.v v12, (a5)
|
|
; RV32-NEXT: vs4r.v v8, (a2)
|
|
; RV32-NEXT: vs8r.v v16, (a1)
|
|
; RV32-NEXT: vl8r.v v16, (a2)
|
|
; RV32-NEXT: vl8r.v v8, (a1)
|
|
; RV32-NEXT: addi sp, s0, -80
|
|
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: addi sp, sp, 80
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vector_interleave_nxv112i8_nxv16i8:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: addi sp, sp, -80
|
|
; RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
|
|
; RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
|
|
; RV64-NEXT: addi s0, sp, 80
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 5
|
|
; RV64-NEXT: sub sp, sp, a0
|
|
; RV64-NEXT: andi sp, sp, -64
|
|
; RV64-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; RV64-NEXT: vmv2r.v v26, v20
|
|
; RV64-NEXT: vmv2r.v v24, v16
|
|
; RV64-NEXT: vmv2r.v v22, v12
|
|
; RV64-NEXT: vmv2r.v v20, v8
|
|
; RV64-NEXT: addi a1, sp, 64
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a2, a0, 3
|
|
; RV64-NEXT: sub a0, a2, a0
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 64
|
|
; RV64-NEXT: csrr a2, vlenb
|
|
; RV64-NEXT: add a3, a1, a2
|
|
; RV64-NEXT: add a4, a0, a2
|
|
; RV64-NEXT: slli a5, a2, 2
|
|
; RV64-NEXT: slli a6, a2, 4
|
|
; RV64-NEXT: add a7, a4, a2
|
|
; RV64-NEXT: sub a5, a6, a5
|
|
; RV64-NEXT: vmv1r.v v1, v20
|
|
; RV64-NEXT: vmv1r.v v3, v22
|
|
; RV64-NEXT: vmv1r.v v5, v24
|
|
; RV64-NEXT: vmv1r.v v7, v26
|
|
; RV64-NEXT: add a6, a7, a2
|
|
; RV64-NEXT: vmv1r.v v2, v10
|
|
; RV64-NEXT: vmv1r.v v4, v14
|
|
; RV64-NEXT: vmv1r.v v6, v18
|
|
; RV64-NEXT: vsseg7e8.v v1, (a1)
|
|
; RV64-NEXT: vmv1r.v v22, v11
|
|
; RV64-NEXT: vmv1r.v v24, v15
|
|
; RV64-NEXT: vmv1r.v v26, v19
|
|
; RV64-NEXT: vsseg7e8.v v21, (a0)
|
|
; RV64-NEXT: vl1r.v v10, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1r.v v11, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1r.v v12, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1r.v v13, (a6)
|
|
; RV64-NEXT: add a6, a3, a2
|
|
; RV64-NEXT: vl1r.v v18, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1r.v v19, (a6)
|
|
; RV64-NEXT: vl1r.v v16, (a1)
|
|
; RV64-NEXT: vl1r.v v8, (a4)
|
|
; RV64-NEXT: vl1r.v v17, (a3)
|
|
; RV64-NEXT: vl1r.v v9, (a7)
|
|
; RV64-NEXT: csrr a1, vlenb
|
|
; RV64-NEXT: li a3, 14
|
|
; RV64-NEXT: mul a1, a1, a3
|
|
; RV64-NEXT: add a1, sp, a1
|
|
; RV64-NEXT: addi a1, a1, 64
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1r.v v20, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1r.v v21, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: slli a2, a2, 3
|
|
; RV64-NEXT: add a2, a1, a2
|
|
; RV64-NEXT: add a5, a1, a5
|
|
; RV64-NEXT: vl1r.v v22, (a6)
|
|
; RV64-NEXT: vl1r.v v23, (a0)
|
|
; RV64-NEXT: vs2r.v v12, (a5)
|
|
; RV64-NEXT: vs4r.v v8, (a2)
|
|
; RV64-NEXT: vs8r.v v16, (a1)
|
|
; RV64-NEXT: vl8r.v v16, (a2)
|
|
; RV64-NEXT: vl8r.v v8, (a1)
|
|
; RV64-NEXT: addi sp, s0, -80
|
|
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
|
|
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
|
|
; RV64-NEXT: addi sp, sp, 80
|
|
; RV64-NEXT: ret
|
|
;
|
|
; ZVBB-RV32-LABEL: vector_interleave_nxv112i8_nxv16i8:
|
|
; ZVBB-RV32: # %bb.0:
|
|
; ZVBB-RV32-NEXT: addi sp, sp, -80
|
|
; ZVBB-RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
|
|
; ZVBB-RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
|
|
; ZVBB-RV32-NEXT: addi s0, sp, 80
|
|
; ZVBB-RV32-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV32-NEXT: slli a0, a0, 5
|
|
; ZVBB-RV32-NEXT: sub sp, sp, a0
|
|
; ZVBB-RV32-NEXT: andi sp, sp, -64
|
|
; ZVBB-RV32-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; ZVBB-RV32-NEXT: vmv2r.v v26, v20
|
|
; ZVBB-RV32-NEXT: vmv2r.v v24, v16
|
|
; ZVBB-RV32-NEXT: vmv2r.v v22, v12
|
|
; ZVBB-RV32-NEXT: vmv2r.v v20, v8
|
|
; ZVBB-RV32-NEXT: addi a1, sp, 64
|
|
; ZVBB-RV32-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV32-NEXT: slli a2, a0, 3
|
|
; ZVBB-RV32-NEXT: sub a0, a2, a0
|
|
; ZVBB-RV32-NEXT: add a0, sp, a0
|
|
; ZVBB-RV32-NEXT: addi a0, a0, 64
|
|
; ZVBB-RV32-NEXT: csrr a2, vlenb
|
|
; ZVBB-RV32-NEXT: add a3, a1, a2
|
|
; ZVBB-RV32-NEXT: add a4, a0, a2
|
|
; ZVBB-RV32-NEXT: slli a5, a2, 2
|
|
; ZVBB-RV32-NEXT: slli a6, a2, 4
|
|
; ZVBB-RV32-NEXT: add a7, a4, a2
|
|
; ZVBB-RV32-NEXT: sub a5, a6, a5
|
|
; ZVBB-RV32-NEXT: vmv1r.v v1, v20
|
|
; ZVBB-RV32-NEXT: vmv1r.v v3, v22
|
|
; ZVBB-RV32-NEXT: vmv1r.v v5, v24
|
|
; ZVBB-RV32-NEXT: vmv1r.v v7, v26
|
|
; ZVBB-RV32-NEXT: add a6, a7, a2
|
|
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
|
|
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
|
|
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
|
|
; ZVBB-RV32-NEXT: vsseg7e8.v v1, (a1)
|
|
; ZVBB-RV32-NEXT: vmv1r.v v22, v11
|
|
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
|
|
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
|
|
; ZVBB-RV32-NEXT: vsseg7e8.v v21, (a0)
|
|
; ZVBB-RV32-NEXT: vl1r.v v10, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1r.v v11, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1r.v v12, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1r.v v13, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a3, a2
|
|
; ZVBB-RV32-NEXT: vl1r.v v18, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1r.v v19, (a6)
|
|
; ZVBB-RV32-NEXT: vl1r.v v16, (a1)
|
|
; ZVBB-RV32-NEXT: vl1r.v v8, (a4)
|
|
; ZVBB-RV32-NEXT: vl1r.v v17, (a3)
|
|
; ZVBB-RV32-NEXT: vl1r.v v9, (a7)
|
|
; ZVBB-RV32-NEXT: csrr a1, vlenb
|
|
; ZVBB-RV32-NEXT: li a3, 14
|
|
; ZVBB-RV32-NEXT: mul a1, a1, a3
|
|
; ZVBB-RV32-NEXT: add a1, sp, a1
|
|
; ZVBB-RV32-NEXT: addi a1, a1, 64
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1r.v v20, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1r.v v21, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: slli a2, a2, 3
|
|
; ZVBB-RV32-NEXT: add a2, a1, a2
|
|
; ZVBB-RV32-NEXT: add a5, a1, a5
|
|
; ZVBB-RV32-NEXT: vl1r.v v22, (a6)
|
|
; ZVBB-RV32-NEXT: vl1r.v v23, (a0)
|
|
; ZVBB-RV32-NEXT: vs2r.v v12, (a5)
|
|
; ZVBB-RV32-NEXT: vs4r.v v8, (a2)
|
|
; ZVBB-RV32-NEXT: vs8r.v v16, (a1)
|
|
; ZVBB-RV32-NEXT: vl8r.v v16, (a2)
|
|
; ZVBB-RV32-NEXT: vl8r.v v8, (a1)
|
|
; ZVBB-RV32-NEXT: addi sp, s0, -80
|
|
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
|
|
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
|
|
; ZVBB-RV32-NEXT: addi sp, sp, 80
|
|
; ZVBB-RV32-NEXT: ret
|
|
;
|
|
; ZVBB-RV64-LABEL: vector_interleave_nxv112i8_nxv16i8:
|
|
; ZVBB-RV64: # %bb.0:
|
|
; ZVBB-RV64-NEXT: addi sp, sp, -80
|
|
; ZVBB-RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
|
|
; ZVBB-RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
|
|
; ZVBB-RV64-NEXT: addi s0, sp, 80
|
|
; ZVBB-RV64-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV64-NEXT: slli a0, a0, 5
|
|
; ZVBB-RV64-NEXT: sub sp, sp, a0
|
|
; ZVBB-RV64-NEXT: andi sp, sp, -64
|
|
; ZVBB-RV64-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; ZVBB-RV64-NEXT: vmv2r.v v26, v20
|
|
; ZVBB-RV64-NEXT: vmv2r.v v24, v16
|
|
; ZVBB-RV64-NEXT: vmv2r.v v22, v12
|
|
; ZVBB-RV64-NEXT: vmv2r.v v20, v8
|
|
; ZVBB-RV64-NEXT: addi a1, sp, 64
|
|
; ZVBB-RV64-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV64-NEXT: slli a2, a0, 3
|
|
; ZVBB-RV64-NEXT: sub a0, a2, a0
|
|
; ZVBB-RV64-NEXT: add a0, sp, a0
|
|
; ZVBB-RV64-NEXT: addi a0, a0, 64
|
|
; ZVBB-RV64-NEXT: csrr a2, vlenb
|
|
; ZVBB-RV64-NEXT: add a3, a1, a2
|
|
; ZVBB-RV64-NEXT: add a4, a0, a2
|
|
; ZVBB-RV64-NEXT: slli a5, a2, 2
|
|
; ZVBB-RV64-NEXT: slli a6, a2, 4
|
|
; ZVBB-RV64-NEXT: add a7, a4, a2
|
|
; ZVBB-RV64-NEXT: sub a5, a6, a5
|
|
; ZVBB-RV64-NEXT: vmv1r.v v1, v20
|
|
; ZVBB-RV64-NEXT: vmv1r.v v3, v22
|
|
; ZVBB-RV64-NEXT: vmv1r.v v5, v24
|
|
; ZVBB-RV64-NEXT: vmv1r.v v7, v26
|
|
; ZVBB-RV64-NEXT: add a6, a7, a2
|
|
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
|
|
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
|
|
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
|
|
; ZVBB-RV64-NEXT: vsseg7e8.v v1, (a1)
|
|
; ZVBB-RV64-NEXT: vmv1r.v v22, v11
|
|
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
|
|
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
|
|
; ZVBB-RV64-NEXT: vsseg7e8.v v21, (a0)
|
|
; ZVBB-RV64-NEXT: vl1r.v v10, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1r.v v11, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1r.v v12, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1r.v v13, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a3, a2
|
|
; ZVBB-RV64-NEXT: vl1r.v v18, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1r.v v19, (a6)
|
|
; ZVBB-RV64-NEXT: vl1r.v v16, (a1)
|
|
; ZVBB-RV64-NEXT: vl1r.v v8, (a4)
|
|
; ZVBB-RV64-NEXT: vl1r.v v17, (a3)
|
|
; ZVBB-RV64-NEXT: vl1r.v v9, (a7)
|
|
; ZVBB-RV64-NEXT: csrr a1, vlenb
|
|
; ZVBB-RV64-NEXT: li a3, 14
|
|
; ZVBB-RV64-NEXT: mul a1, a1, a3
|
|
; ZVBB-RV64-NEXT: add a1, sp, a1
|
|
; ZVBB-RV64-NEXT: addi a1, a1, 64
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1r.v v20, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1r.v v21, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: slli a2, a2, 3
|
|
; ZVBB-RV64-NEXT: add a2, a1, a2
|
|
; ZVBB-RV64-NEXT: add a5, a1, a5
|
|
; ZVBB-RV64-NEXT: vl1r.v v22, (a6)
|
|
; ZVBB-RV64-NEXT: vl1r.v v23, (a0)
|
|
; ZVBB-RV64-NEXT: vs2r.v v12, (a5)
|
|
; ZVBB-RV64-NEXT: vs4r.v v8, (a2)
|
|
; ZVBB-RV64-NEXT: vs8r.v v16, (a1)
|
|
; ZVBB-RV64-NEXT: vl8r.v v16, (a2)
|
|
; ZVBB-RV64-NEXT: vl8r.v v8, (a1)
|
|
; ZVBB-RV64-NEXT: addi sp, s0, -80
|
|
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
|
|
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
|
|
; ZVBB-RV64-NEXT: addi sp, sp, 80
|
|
; ZVBB-RV64-NEXT: ret
|
|
%res = call <vscale x 112 x i8> @llvm.vector.interleave7.nxv112i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e, <vscale x 16 x i8> %f, <vscale x 16 x i8> %g)
|
|
ret <vscale x 112 x i8> %res
|
|
}
|
|
|
|
|
|
define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i16> %d, <vscale x 8 x i16> %e, <vscale x 8 x i16> %f, <vscale x 8 x i16> %g) nounwind {
|
|
;
|
|
; RV32-LABEL: vector_interleave_nxv56i16_nxv8i16:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi sp, sp, -80
|
|
; RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: addi s0, sp, 80
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 5
|
|
; RV32-NEXT: sub sp, sp, a0
|
|
; RV32-NEXT: andi sp, sp, -64
|
|
; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; RV32-NEXT: vmv2r.v v26, v20
|
|
; RV32-NEXT: vmv2r.v v24, v16
|
|
; RV32-NEXT: vmv2r.v v22, v12
|
|
; RV32-NEXT: vmv2r.v v20, v8
|
|
; RV32-NEXT: addi a1, sp, 64
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a2, a0, 3
|
|
; RV32-NEXT: sub a0, a2, a0
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 64
|
|
; RV32-NEXT: csrr a2, vlenb
|
|
; RV32-NEXT: add a3, a1, a2
|
|
; RV32-NEXT: add a4, a0, a2
|
|
; RV32-NEXT: slli a5, a2, 2
|
|
; RV32-NEXT: slli a6, a2, 4
|
|
; RV32-NEXT: add a7, a4, a2
|
|
; RV32-NEXT: sub a5, a6, a5
|
|
; RV32-NEXT: vmv1r.v v1, v20
|
|
; RV32-NEXT: vmv1r.v v3, v22
|
|
; RV32-NEXT: vmv1r.v v5, v24
|
|
; RV32-NEXT: vmv1r.v v7, v26
|
|
; RV32-NEXT: add a6, a7, a2
|
|
; RV32-NEXT: vmv1r.v v2, v10
|
|
; RV32-NEXT: vmv1r.v v4, v14
|
|
; RV32-NEXT: vmv1r.v v6, v18
|
|
; RV32-NEXT: vsseg7e16.v v1, (a1)
|
|
; RV32-NEXT: vmv1r.v v22, v11
|
|
; RV32-NEXT: vmv1r.v v24, v15
|
|
; RV32-NEXT: vmv1r.v v26, v19
|
|
; RV32-NEXT: vsseg7e16.v v21, (a0)
|
|
; RV32-NEXT: vl1re16.v v10, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re16.v v11, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re16.v v12, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re16.v v13, (a6)
|
|
; RV32-NEXT: add a6, a3, a2
|
|
; RV32-NEXT: vl1re16.v v18, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re16.v v19, (a6)
|
|
; RV32-NEXT: vl1re16.v v16, (a1)
|
|
; RV32-NEXT: vl1re16.v v8, (a4)
|
|
; RV32-NEXT: vl1re16.v v17, (a3)
|
|
; RV32-NEXT: vl1re16.v v9, (a7)
|
|
; RV32-NEXT: csrr a1, vlenb
|
|
; RV32-NEXT: li a3, 14
|
|
; RV32-NEXT: mul a1, a1, a3
|
|
; RV32-NEXT: add a1, sp, a1
|
|
; RV32-NEXT: addi a1, a1, 64
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re16.v v20, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re16.v v21, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: slli a2, a2, 3
|
|
; RV32-NEXT: add a2, a1, a2
|
|
; RV32-NEXT: add a5, a1, a5
|
|
; RV32-NEXT: vl1re16.v v22, (a6)
|
|
; RV32-NEXT: vl1re16.v v23, (a0)
|
|
; RV32-NEXT: vs2r.v v12, (a5)
|
|
; RV32-NEXT: vs4r.v v8, (a2)
|
|
; RV32-NEXT: vs8r.v v16, (a1)
|
|
; RV32-NEXT: vl8re16.v v16, (a2)
|
|
; RV32-NEXT: vl8re16.v v8, (a1)
|
|
; RV32-NEXT: addi sp, s0, -80
|
|
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: addi sp, sp, 80
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vector_interleave_nxv56i16_nxv8i16:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: addi sp, sp, -80
|
|
; RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
|
|
; RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
|
|
; RV64-NEXT: addi s0, sp, 80
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 5
|
|
; RV64-NEXT: sub sp, sp, a0
|
|
; RV64-NEXT: andi sp, sp, -64
|
|
; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; RV64-NEXT: vmv2r.v v26, v20
|
|
; RV64-NEXT: vmv2r.v v24, v16
|
|
; RV64-NEXT: vmv2r.v v22, v12
|
|
; RV64-NEXT: vmv2r.v v20, v8
|
|
; RV64-NEXT: addi a1, sp, 64
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a2, a0, 3
|
|
; RV64-NEXT: sub a0, a2, a0
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 64
|
|
; RV64-NEXT: csrr a2, vlenb
|
|
; RV64-NEXT: add a3, a1, a2
|
|
; RV64-NEXT: add a4, a0, a2
|
|
; RV64-NEXT: slli a5, a2, 2
|
|
; RV64-NEXT: slli a6, a2, 4
|
|
; RV64-NEXT: add a7, a4, a2
|
|
; RV64-NEXT: sub a5, a6, a5
|
|
; RV64-NEXT: vmv1r.v v1, v20
|
|
; RV64-NEXT: vmv1r.v v3, v22
|
|
; RV64-NEXT: vmv1r.v v5, v24
|
|
; RV64-NEXT: vmv1r.v v7, v26
|
|
; RV64-NEXT: add a6, a7, a2
|
|
; RV64-NEXT: vmv1r.v v2, v10
|
|
; RV64-NEXT: vmv1r.v v4, v14
|
|
; RV64-NEXT: vmv1r.v v6, v18
|
|
; RV64-NEXT: vsseg7e16.v v1, (a1)
|
|
; RV64-NEXT: vmv1r.v v22, v11
|
|
; RV64-NEXT: vmv1r.v v24, v15
|
|
; RV64-NEXT: vmv1r.v v26, v19
|
|
; RV64-NEXT: vsseg7e16.v v21, (a0)
|
|
; RV64-NEXT: vl1re16.v v10, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re16.v v11, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re16.v v12, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re16.v v13, (a6)
|
|
; RV64-NEXT: add a6, a3, a2
|
|
; RV64-NEXT: vl1re16.v v18, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re16.v v19, (a6)
|
|
; RV64-NEXT: vl1re16.v v16, (a1)
|
|
; RV64-NEXT: vl1re16.v v8, (a4)
|
|
; RV64-NEXT: vl1re16.v v17, (a3)
|
|
; RV64-NEXT: vl1re16.v v9, (a7)
|
|
; RV64-NEXT: csrr a1, vlenb
|
|
; RV64-NEXT: li a3, 14
|
|
; RV64-NEXT: mul a1, a1, a3
|
|
; RV64-NEXT: add a1, sp, a1
|
|
; RV64-NEXT: addi a1, a1, 64
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re16.v v20, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re16.v v21, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: slli a2, a2, 3
|
|
; RV64-NEXT: add a2, a1, a2
|
|
; RV64-NEXT: add a5, a1, a5
|
|
; RV64-NEXT: vl1re16.v v22, (a6)
|
|
; RV64-NEXT: vl1re16.v v23, (a0)
|
|
; RV64-NEXT: vs2r.v v12, (a5)
|
|
; RV64-NEXT: vs4r.v v8, (a2)
|
|
; RV64-NEXT: vs8r.v v16, (a1)
|
|
; RV64-NEXT: vl8re16.v v16, (a2)
|
|
; RV64-NEXT: vl8re16.v v8, (a1)
|
|
; RV64-NEXT: addi sp, s0, -80
|
|
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
|
|
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
|
|
; RV64-NEXT: addi sp, sp, 80
|
|
; RV64-NEXT: ret
|
|
;
|
|
; ZVBB-RV32-LABEL: vector_interleave_nxv56i16_nxv8i16:
|
|
; ZVBB-RV32: # %bb.0:
|
|
; ZVBB-RV32-NEXT: addi sp, sp, -80
|
|
; ZVBB-RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
|
|
; ZVBB-RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
|
|
; ZVBB-RV32-NEXT: addi s0, sp, 80
|
|
; ZVBB-RV32-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV32-NEXT: slli a0, a0, 5
|
|
; ZVBB-RV32-NEXT: sub sp, sp, a0
|
|
; ZVBB-RV32-NEXT: andi sp, sp, -64
|
|
; ZVBB-RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; ZVBB-RV32-NEXT: vmv2r.v v26, v20
|
|
; ZVBB-RV32-NEXT: vmv2r.v v24, v16
|
|
; ZVBB-RV32-NEXT: vmv2r.v v22, v12
|
|
; ZVBB-RV32-NEXT: vmv2r.v v20, v8
|
|
; ZVBB-RV32-NEXT: addi a1, sp, 64
|
|
; ZVBB-RV32-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV32-NEXT: slli a2, a0, 3
|
|
; ZVBB-RV32-NEXT: sub a0, a2, a0
|
|
; ZVBB-RV32-NEXT: add a0, sp, a0
|
|
; ZVBB-RV32-NEXT: addi a0, a0, 64
|
|
; ZVBB-RV32-NEXT: csrr a2, vlenb
|
|
; ZVBB-RV32-NEXT: add a3, a1, a2
|
|
; ZVBB-RV32-NEXT: add a4, a0, a2
|
|
; ZVBB-RV32-NEXT: slli a5, a2, 2
|
|
; ZVBB-RV32-NEXT: slli a6, a2, 4
|
|
; ZVBB-RV32-NEXT: add a7, a4, a2
|
|
; ZVBB-RV32-NEXT: sub a5, a6, a5
|
|
; ZVBB-RV32-NEXT: vmv1r.v v1, v20
|
|
; ZVBB-RV32-NEXT: vmv1r.v v3, v22
|
|
; ZVBB-RV32-NEXT: vmv1r.v v5, v24
|
|
; ZVBB-RV32-NEXT: vmv1r.v v7, v26
|
|
; ZVBB-RV32-NEXT: add a6, a7, a2
|
|
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
|
|
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
|
|
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
|
|
; ZVBB-RV32-NEXT: vsseg7e16.v v1, (a1)
|
|
; ZVBB-RV32-NEXT: vmv1r.v v22, v11
|
|
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
|
|
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
|
|
; ZVBB-RV32-NEXT: vsseg7e16.v v21, (a0)
|
|
; ZVBB-RV32-NEXT: vl1re16.v v10, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re16.v v11, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re16.v v12, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re16.v v13, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a3, a2
|
|
; ZVBB-RV32-NEXT: vl1re16.v v18, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re16.v v19, (a6)
|
|
; ZVBB-RV32-NEXT: vl1re16.v v16, (a1)
|
|
; ZVBB-RV32-NEXT: vl1re16.v v8, (a4)
|
|
; ZVBB-RV32-NEXT: vl1re16.v v17, (a3)
|
|
; ZVBB-RV32-NEXT: vl1re16.v v9, (a7)
|
|
; ZVBB-RV32-NEXT: csrr a1, vlenb
|
|
; ZVBB-RV32-NEXT: li a3, 14
|
|
; ZVBB-RV32-NEXT: mul a1, a1, a3
|
|
; ZVBB-RV32-NEXT: add a1, sp, a1
|
|
; ZVBB-RV32-NEXT: addi a1, a1, 64
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re16.v v20, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re16.v v21, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: slli a2, a2, 3
|
|
; ZVBB-RV32-NEXT: add a2, a1, a2
|
|
; ZVBB-RV32-NEXT: add a5, a1, a5
|
|
; ZVBB-RV32-NEXT: vl1re16.v v22, (a6)
|
|
; ZVBB-RV32-NEXT: vl1re16.v v23, (a0)
|
|
; ZVBB-RV32-NEXT: vs2r.v v12, (a5)
|
|
; ZVBB-RV32-NEXT: vs4r.v v8, (a2)
|
|
; ZVBB-RV32-NEXT: vs8r.v v16, (a1)
|
|
; ZVBB-RV32-NEXT: vl8re16.v v16, (a2)
|
|
; ZVBB-RV32-NEXT: vl8re16.v v8, (a1)
|
|
; ZVBB-RV32-NEXT: addi sp, s0, -80
|
|
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
|
|
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
|
|
; ZVBB-RV32-NEXT: addi sp, sp, 80
|
|
; ZVBB-RV32-NEXT: ret
|
|
;
|
|
; ZVBB-RV64-LABEL: vector_interleave_nxv56i16_nxv8i16:
|
|
; ZVBB-RV64: # %bb.0:
|
|
; ZVBB-RV64-NEXT: addi sp, sp, -80
|
|
; ZVBB-RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
|
|
; ZVBB-RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
|
|
; ZVBB-RV64-NEXT: addi s0, sp, 80
|
|
; ZVBB-RV64-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV64-NEXT: slli a0, a0, 5
|
|
; ZVBB-RV64-NEXT: sub sp, sp, a0
|
|
; ZVBB-RV64-NEXT: andi sp, sp, -64
|
|
; ZVBB-RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; ZVBB-RV64-NEXT: vmv2r.v v26, v20
|
|
; ZVBB-RV64-NEXT: vmv2r.v v24, v16
|
|
; ZVBB-RV64-NEXT: vmv2r.v v22, v12
|
|
; ZVBB-RV64-NEXT: vmv2r.v v20, v8
|
|
; ZVBB-RV64-NEXT: addi a1, sp, 64
|
|
; ZVBB-RV64-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV64-NEXT: slli a2, a0, 3
|
|
; ZVBB-RV64-NEXT: sub a0, a2, a0
|
|
; ZVBB-RV64-NEXT: add a0, sp, a0
|
|
; ZVBB-RV64-NEXT: addi a0, a0, 64
|
|
; ZVBB-RV64-NEXT: csrr a2, vlenb
|
|
; ZVBB-RV64-NEXT: add a3, a1, a2
|
|
; ZVBB-RV64-NEXT: add a4, a0, a2
|
|
; ZVBB-RV64-NEXT: slli a5, a2, 2
|
|
; ZVBB-RV64-NEXT: slli a6, a2, 4
|
|
; ZVBB-RV64-NEXT: add a7, a4, a2
|
|
; ZVBB-RV64-NEXT: sub a5, a6, a5
|
|
; ZVBB-RV64-NEXT: vmv1r.v v1, v20
|
|
; ZVBB-RV64-NEXT: vmv1r.v v3, v22
|
|
; ZVBB-RV64-NEXT: vmv1r.v v5, v24
|
|
; ZVBB-RV64-NEXT: vmv1r.v v7, v26
|
|
; ZVBB-RV64-NEXT: add a6, a7, a2
|
|
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
|
|
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
|
|
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
|
|
; ZVBB-RV64-NEXT: vsseg7e16.v v1, (a1)
|
|
; ZVBB-RV64-NEXT: vmv1r.v v22, v11
|
|
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
|
|
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
|
|
; ZVBB-RV64-NEXT: vsseg7e16.v v21, (a0)
|
|
; ZVBB-RV64-NEXT: vl1re16.v v10, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re16.v v11, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re16.v v12, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re16.v v13, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a3, a2
|
|
; ZVBB-RV64-NEXT: vl1re16.v v18, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re16.v v19, (a6)
|
|
; ZVBB-RV64-NEXT: vl1re16.v v16, (a1)
|
|
; ZVBB-RV64-NEXT: vl1re16.v v8, (a4)
|
|
; ZVBB-RV64-NEXT: vl1re16.v v17, (a3)
|
|
; ZVBB-RV64-NEXT: vl1re16.v v9, (a7)
|
|
; ZVBB-RV64-NEXT: csrr a1, vlenb
|
|
; ZVBB-RV64-NEXT: li a3, 14
|
|
; ZVBB-RV64-NEXT: mul a1, a1, a3
|
|
; ZVBB-RV64-NEXT: add a1, sp, a1
|
|
; ZVBB-RV64-NEXT: addi a1, a1, 64
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re16.v v20, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re16.v v21, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: slli a2, a2, 3
|
|
; ZVBB-RV64-NEXT: add a2, a1, a2
|
|
; ZVBB-RV64-NEXT: add a5, a1, a5
|
|
; ZVBB-RV64-NEXT: vl1re16.v v22, (a6)
|
|
; ZVBB-RV64-NEXT: vl1re16.v v23, (a0)
|
|
; ZVBB-RV64-NEXT: vs2r.v v12, (a5)
|
|
; ZVBB-RV64-NEXT: vs4r.v v8, (a2)
|
|
; ZVBB-RV64-NEXT: vs8r.v v16, (a1)
|
|
; ZVBB-RV64-NEXT: vl8re16.v v16, (a2)
|
|
; ZVBB-RV64-NEXT: vl8re16.v v8, (a1)
|
|
; ZVBB-RV64-NEXT: addi sp, s0, -80
|
|
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
|
|
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
|
|
; ZVBB-RV64-NEXT: addi sp, sp, 80
|
|
; ZVBB-RV64-NEXT: ret
|
|
%res = call <vscale x 56 x i16> @llvm.vector.interleave7.nxv56i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i16> %d, <vscale x 8 x i16> %e, <vscale x 8 x i16> %f, <vscale x 8 x i16> %g)
|
|
ret <vscale x 56 x i16> %res
|
|
}
|
|
|
|
|
|
define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e, <vscale x 4 x i32> %f, <vscale x 4 x i32> %g) nounwind {
|
|
;
|
|
; RV32-LABEL: vector_interleave_nxv28i32_nxv4i32:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi sp, sp, -80
|
|
; RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: addi s0, sp, 80
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 5
|
|
; RV32-NEXT: sub sp, sp, a0
|
|
; RV32-NEXT: andi sp, sp, -64
|
|
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; RV32-NEXT: vmv2r.v v26, v20
|
|
; RV32-NEXT: vmv2r.v v24, v16
|
|
; RV32-NEXT: vmv2r.v v22, v12
|
|
; RV32-NEXT: vmv2r.v v20, v8
|
|
; RV32-NEXT: addi a1, sp, 64
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a2, a0, 3
|
|
; RV32-NEXT: sub a0, a2, a0
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 64
|
|
; RV32-NEXT: csrr a2, vlenb
|
|
; RV32-NEXT: add a3, a1, a2
|
|
; RV32-NEXT: add a4, a0, a2
|
|
; RV32-NEXT: slli a5, a2, 2
|
|
; RV32-NEXT: slli a6, a2, 4
|
|
; RV32-NEXT: add a7, a4, a2
|
|
; RV32-NEXT: sub a5, a6, a5
|
|
; RV32-NEXT: vmv1r.v v1, v20
|
|
; RV32-NEXT: vmv1r.v v3, v22
|
|
; RV32-NEXT: vmv1r.v v5, v24
|
|
; RV32-NEXT: vmv1r.v v7, v26
|
|
; RV32-NEXT: add a6, a7, a2
|
|
; RV32-NEXT: vmv1r.v v2, v10
|
|
; RV32-NEXT: vmv1r.v v4, v14
|
|
; RV32-NEXT: vmv1r.v v6, v18
|
|
; RV32-NEXT: vsseg7e32.v v1, (a1)
|
|
; RV32-NEXT: vmv1r.v v22, v11
|
|
; RV32-NEXT: vmv1r.v v24, v15
|
|
; RV32-NEXT: vmv1r.v v26, v19
|
|
; RV32-NEXT: vsseg7e32.v v21, (a0)
|
|
; RV32-NEXT: vl1re32.v v10, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re32.v v11, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re32.v v12, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re32.v v13, (a6)
|
|
; RV32-NEXT: add a6, a3, a2
|
|
; RV32-NEXT: vl1re32.v v18, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re32.v v19, (a6)
|
|
; RV32-NEXT: vl1re32.v v16, (a1)
|
|
; RV32-NEXT: vl1re32.v v8, (a4)
|
|
; RV32-NEXT: vl1re32.v v17, (a3)
|
|
; RV32-NEXT: vl1re32.v v9, (a7)
|
|
; RV32-NEXT: csrr a1, vlenb
|
|
; RV32-NEXT: li a3, 14
|
|
; RV32-NEXT: mul a1, a1, a3
|
|
; RV32-NEXT: add a1, sp, a1
|
|
; RV32-NEXT: addi a1, a1, 64
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re32.v v20, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re32.v v21, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: slli a2, a2, 3
|
|
; RV32-NEXT: add a2, a1, a2
|
|
; RV32-NEXT: add a5, a1, a5
|
|
; RV32-NEXT: vl1re32.v v22, (a6)
|
|
; RV32-NEXT: vl1re32.v v23, (a0)
|
|
; RV32-NEXT: vs2r.v v12, (a5)
|
|
; RV32-NEXT: vs4r.v v8, (a2)
|
|
; RV32-NEXT: vs8r.v v16, (a1)
|
|
; RV32-NEXT: vl8re32.v v16, (a2)
|
|
; RV32-NEXT: vl8re32.v v8, (a1)
|
|
; RV32-NEXT: addi sp, s0, -80
|
|
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: addi sp, sp, 80
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vector_interleave_nxv28i32_nxv4i32:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: addi sp, sp, -80
|
|
; RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
|
|
; RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
|
|
; RV64-NEXT: addi s0, sp, 80
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 5
|
|
; RV64-NEXT: sub sp, sp, a0
|
|
; RV64-NEXT: andi sp, sp, -64
|
|
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; RV64-NEXT: vmv2r.v v26, v20
|
|
; RV64-NEXT: vmv2r.v v24, v16
|
|
; RV64-NEXT: vmv2r.v v22, v12
|
|
; RV64-NEXT: vmv2r.v v20, v8
|
|
; RV64-NEXT: addi a1, sp, 64
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a2, a0, 3
|
|
; RV64-NEXT: sub a0, a2, a0
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 64
|
|
; RV64-NEXT: csrr a2, vlenb
|
|
; RV64-NEXT: add a3, a1, a2
|
|
; RV64-NEXT: add a4, a0, a2
|
|
; RV64-NEXT: slli a5, a2, 2
|
|
; RV64-NEXT: slli a6, a2, 4
|
|
; RV64-NEXT: add a7, a4, a2
|
|
; RV64-NEXT: sub a5, a6, a5
|
|
; RV64-NEXT: vmv1r.v v1, v20
|
|
; RV64-NEXT: vmv1r.v v3, v22
|
|
; RV64-NEXT: vmv1r.v v5, v24
|
|
; RV64-NEXT: vmv1r.v v7, v26
|
|
; RV64-NEXT: add a6, a7, a2
|
|
; RV64-NEXT: vmv1r.v v2, v10
|
|
; RV64-NEXT: vmv1r.v v4, v14
|
|
; RV64-NEXT: vmv1r.v v6, v18
|
|
; RV64-NEXT: vsseg7e32.v v1, (a1)
|
|
; RV64-NEXT: vmv1r.v v22, v11
|
|
; RV64-NEXT: vmv1r.v v24, v15
|
|
; RV64-NEXT: vmv1r.v v26, v19
|
|
; RV64-NEXT: vsseg7e32.v v21, (a0)
|
|
; RV64-NEXT: vl1re32.v v10, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re32.v v11, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re32.v v12, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re32.v v13, (a6)
|
|
; RV64-NEXT: add a6, a3, a2
|
|
; RV64-NEXT: vl1re32.v v18, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re32.v v19, (a6)
|
|
; RV64-NEXT: vl1re32.v v16, (a1)
|
|
; RV64-NEXT: vl1re32.v v8, (a4)
|
|
; RV64-NEXT: vl1re32.v v17, (a3)
|
|
; RV64-NEXT: vl1re32.v v9, (a7)
|
|
; RV64-NEXT: csrr a1, vlenb
|
|
; RV64-NEXT: li a3, 14
|
|
; RV64-NEXT: mul a1, a1, a3
|
|
; RV64-NEXT: add a1, sp, a1
|
|
; RV64-NEXT: addi a1, a1, 64
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re32.v v20, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re32.v v21, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: slli a2, a2, 3
|
|
; RV64-NEXT: add a2, a1, a2
|
|
; RV64-NEXT: add a5, a1, a5
|
|
; RV64-NEXT: vl1re32.v v22, (a6)
|
|
; RV64-NEXT: vl1re32.v v23, (a0)
|
|
; RV64-NEXT: vs2r.v v12, (a5)
|
|
; RV64-NEXT: vs4r.v v8, (a2)
|
|
; RV64-NEXT: vs8r.v v16, (a1)
|
|
; RV64-NEXT: vl8re32.v v16, (a2)
|
|
; RV64-NEXT: vl8re32.v v8, (a1)
|
|
; RV64-NEXT: addi sp, s0, -80
|
|
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
|
|
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
|
|
; RV64-NEXT: addi sp, sp, 80
|
|
; RV64-NEXT: ret
|
|
;
|
|
; ZVBB-RV32-LABEL: vector_interleave_nxv28i32_nxv4i32:
|
|
; ZVBB-RV32: # %bb.0:
|
|
; ZVBB-RV32-NEXT: addi sp, sp, -80
|
|
; ZVBB-RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
|
|
; ZVBB-RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
|
|
; ZVBB-RV32-NEXT: addi s0, sp, 80
|
|
; ZVBB-RV32-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV32-NEXT: slli a0, a0, 5
|
|
; ZVBB-RV32-NEXT: sub sp, sp, a0
|
|
; ZVBB-RV32-NEXT: andi sp, sp, -64
|
|
; ZVBB-RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; ZVBB-RV32-NEXT: vmv2r.v v26, v20
|
|
; ZVBB-RV32-NEXT: vmv2r.v v24, v16
|
|
; ZVBB-RV32-NEXT: vmv2r.v v22, v12
|
|
; ZVBB-RV32-NEXT: vmv2r.v v20, v8
|
|
; ZVBB-RV32-NEXT: addi a1, sp, 64
|
|
; ZVBB-RV32-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV32-NEXT: slli a2, a0, 3
|
|
; ZVBB-RV32-NEXT: sub a0, a2, a0
|
|
; ZVBB-RV32-NEXT: add a0, sp, a0
|
|
; ZVBB-RV32-NEXT: addi a0, a0, 64
|
|
; ZVBB-RV32-NEXT: csrr a2, vlenb
|
|
; ZVBB-RV32-NEXT: add a3, a1, a2
|
|
; ZVBB-RV32-NEXT: add a4, a0, a2
|
|
; ZVBB-RV32-NEXT: slli a5, a2, 2
|
|
; ZVBB-RV32-NEXT: slli a6, a2, 4
|
|
; ZVBB-RV32-NEXT: add a7, a4, a2
|
|
; ZVBB-RV32-NEXT: sub a5, a6, a5
|
|
; ZVBB-RV32-NEXT: vmv1r.v v1, v20
|
|
; ZVBB-RV32-NEXT: vmv1r.v v3, v22
|
|
; ZVBB-RV32-NEXT: vmv1r.v v5, v24
|
|
; ZVBB-RV32-NEXT: vmv1r.v v7, v26
|
|
; ZVBB-RV32-NEXT: add a6, a7, a2
|
|
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
|
|
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
|
|
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
|
|
; ZVBB-RV32-NEXT: vsseg7e32.v v1, (a1)
|
|
; ZVBB-RV32-NEXT: vmv1r.v v22, v11
|
|
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
|
|
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
|
|
; ZVBB-RV32-NEXT: vsseg7e32.v v21, (a0)
|
|
; ZVBB-RV32-NEXT: vl1re32.v v10, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re32.v v11, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re32.v v12, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re32.v v13, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a3, a2
|
|
; ZVBB-RV32-NEXT: vl1re32.v v18, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re32.v v19, (a6)
|
|
; ZVBB-RV32-NEXT: vl1re32.v v16, (a1)
|
|
; ZVBB-RV32-NEXT: vl1re32.v v8, (a4)
|
|
; ZVBB-RV32-NEXT: vl1re32.v v17, (a3)
|
|
; ZVBB-RV32-NEXT: vl1re32.v v9, (a7)
|
|
; ZVBB-RV32-NEXT: csrr a1, vlenb
|
|
; ZVBB-RV32-NEXT: li a3, 14
|
|
; ZVBB-RV32-NEXT: mul a1, a1, a3
|
|
; ZVBB-RV32-NEXT: add a1, sp, a1
|
|
; ZVBB-RV32-NEXT: addi a1, a1, 64
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re32.v v20, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re32.v v21, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: slli a2, a2, 3
|
|
; ZVBB-RV32-NEXT: add a2, a1, a2
|
|
; ZVBB-RV32-NEXT: add a5, a1, a5
|
|
; ZVBB-RV32-NEXT: vl1re32.v v22, (a6)
|
|
; ZVBB-RV32-NEXT: vl1re32.v v23, (a0)
|
|
; ZVBB-RV32-NEXT: vs2r.v v12, (a5)
|
|
; ZVBB-RV32-NEXT: vs4r.v v8, (a2)
|
|
; ZVBB-RV32-NEXT: vs8r.v v16, (a1)
|
|
; ZVBB-RV32-NEXT: vl8re32.v v16, (a2)
|
|
; ZVBB-RV32-NEXT: vl8re32.v v8, (a1)
|
|
; ZVBB-RV32-NEXT: addi sp, s0, -80
|
|
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
|
|
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
|
|
; ZVBB-RV32-NEXT: addi sp, sp, 80
|
|
; ZVBB-RV32-NEXT: ret
|
|
;
|
|
; ZVBB-RV64-LABEL: vector_interleave_nxv28i32_nxv4i32:
|
|
; ZVBB-RV64: # %bb.0:
|
|
; ZVBB-RV64-NEXT: addi sp, sp, -80
|
|
; ZVBB-RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
|
|
; ZVBB-RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
|
|
; ZVBB-RV64-NEXT: addi s0, sp, 80
|
|
; ZVBB-RV64-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV64-NEXT: slli a0, a0, 5
|
|
; ZVBB-RV64-NEXT: sub sp, sp, a0
|
|
; ZVBB-RV64-NEXT: andi sp, sp, -64
|
|
; ZVBB-RV64-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; ZVBB-RV64-NEXT: vmv2r.v v26, v20
|
|
; ZVBB-RV64-NEXT: vmv2r.v v24, v16
|
|
; ZVBB-RV64-NEXT: vmv2r.v v22, v12
|
|
; ZVBB-RV64-NEXT: vmv2r.v v20, v8
|
|
; ZVBB-RV64-NEXT: addi a1, sp, 64
|
|
; ZVBB-RV64-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV64-NEXT: slli a2, a0, 3
|
|
; ZVBB-RV64-NEXT: sub a0, a2, a0
|
|
; ZVBB-RV64-NEXT: add a0, sp, a0
|
|
; ZVBB-RV64-NEXT: addi a0, a0, 64
|
|
; ZVBB-RV64-NEXT: csrr a2, vlenb
|
|
; ZVBB-RV64-NEXT: add a3, a1, a2
|
|
; ZVBB-RV64-NEXT: add a4, a0, a2
|
|
; ZVBB-RV64-NEXT: slli a5, a2, 2
|
|
; ZVBB-RV64-NEXT: slli a6, a2, 4
|
|
; ZVBB-RV64-NEXT: add a7, a4, a2
|
|
; ZVBB-RV64-NEXT: sub a5, a6, a5
|
|
; ZVBB-RV64-NEXT: vmv1r.v v1, v20
|
|
; ZVBB-RV64-NEXT: vmv1r.v v3, v22
|
|
; ZVBB-RV64-NEXT: vmv1r.v v5, v24
|
|
; ZVBB-RV64-NEXT: vmv1r.v v7, v26
|
|
; ZVBB-RV64-NEXT: add a6, a7, a2
|
|
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
|
|
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
|
|
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
|
|
; ZVBB-RV64-NEXT: vsseg7e32.v v1, (a1)
|
|
; ZVBB-RV64-NEXT: vmv1r.v v22, v11
|
|
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
|
|
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
|
|
; ZVBB-RV64-NEXT: vsseg7e32.v v21, (a0)
|
|
; ZVBB-RV64-NEXT: vl1re32.v v10, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re32.v v11, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re32.v v12, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re32.v v13, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a3, a2
|
|
; ZVBB-RV64-NEXT: vl1re32.v v18, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re32.v v19, (a6)
|
|
; ZVBB-RV64-NEXT: vl1re32.v v16, (a1)
|
|
; ZVBB-RV64-NEXT: vl1re32.v v8, (a4)
|
|
; ZVBB-RV64-NEXT: vl1re32.v v17, (a3)
|
|
; ZVBB-RV64-NEXT: vl1re32.v v9, (a7)
|
|
; ZVBB-RV64-NEXT: csrr a1, vlenb
|
|
; ZVBB-RV64-NEXT: li a3, 14
|
|
; ZVBB-RV64-NEXT: mul a1, a1, a3
|
|
; ZVBB-RV64-NEXT: add a1, sp, a1
|
|
; ZVBB-RV64-NEXT: addi a1, a1, 64
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re32.v v20, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re32.v v21, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: slli a2, a2, 3
|
|
; ZVBB-RV64-NEXT: add a2, a1, a2
|
|
; ZVBB-RV64-NEXT: add a5, a1, a5
|
|
; ZVBB-RV64-NEXT: vl1re32.v v22, (a6)
|
|
; ZVBB-RV64-NEXT: vl1re32.v v23, (a0)
|
|
; ZVBB-RV64-NEXT: vs2r.v v12, (a5)
|
|
; ZVBB-RV64-NEXT: vs4r.v v8, (a2)
|
|
; ZVBB-RV64-NEXT: vs8r.v v16, (a1)
|
|
; ZVBB-RV64-NEXT: vl8re32.v v16, (a2)
|
|
; ZVBB-RV64-NEXT: vl8re32.v v8, (a1)
|
|
; ZVBB-RV64-NEXT: addi sp, s0, -80
|
|
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
|
|
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
|
|
; ZVBB-RV64-NEXT: addi sp, sp, 80
|
|
; ZVBB-RV64-NEXT: ret
|
|
%res = call <vscale x 28 x i32> @llvm.vector.interleave7.nxv28i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e, <vscale x 4 x i32> %f, <vscale x 4 x i32> %g)
|
|
ret <vscale x 28 x i32> %res
|
|
}
|
|
|
|
define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e, <vscale x 2 x i64> %f, <vscale x 2 x i64> %g) nounwind {
|
|
;
|
|
; RV32-LABEL: vector_interleave_nxv14i64_nxv2i64:
|
|
; RV32: # %bb.0:
|
|
; RV32-NEXT: addi sp, sp, -80
|
|
; RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
|
|
; RV32-NEXT: addi s0, sp, 80
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a0, a0, 5
|
|
; RV32-NEXT: sub sp, sp, a0
|
|
; RV32-NEXT: andi sp, sp, -64
|
|
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; RV32-NEXT: vmv2r.v v26, v20
|
|
; RV32-NEXT: vmv2r.v v24, v16
|
|
; RV32-NEXT: vmv2r.v v22, v12
|
|
; RV32-NEXT: vmv2r.v v20, v8
|
|
; RV32-NEXT: addi a1, sp, 64
|
|
; RV32-NEXT: csrr a0, vlenb
|
|
; RV32-NEXT: slli a2, a0, 3
|
|
; RV32-NEXT: sub a0, a2, a0
|
|
; RV32-NEXT: add a0, sp, a0
|
|
; RV32-NEXT: addi a0, a0, 64
|
|
; RV32-NEXT: csrr a2, vlenb
|
|
; RV32-NEXT: add a3, a1, a2
|
|
; RV32-NEXT: add a4, a0, a2
|
|
; RV32-NEXT: slli a5, a2, 2
|
|
; RV32-NEXT: slli a6, a2, 4
|
|
; RV32-NEXT: add a7, a4, a2
|
|
; RV32-NEXT: sub a5, a6, a5
|
|
; RV32-NEXT: vmv1r.v v1, v20
|
|
; RV32-NEXT: vmv1r.v v3, v22
|
|
; RV32-NEXT: vmv1r.v v5, v24
|
|
; RV32-NEXT: vmv1r.v v7, v26
|
|
; RV32-NEXT: add a6, a7, a2
|
|
; RV32-NEXT: vmv1r.v v2, v10
|
|
; RV32-NEXT: vmv1r.v v4, v14
|
|
; RV32-NEXT: vmv1r.v v6, v18
|
|
; RV32-NEXT: vsseg7e64.v v1, (a1)
|
|
; RV32-NEXT: vmv1r.v v22, v11
|
|
; RV32-NEXT: vmv1r.v v24, v15
|
|
; RV32-NEXT: vmv1r.v v26, v19
|
|
; RV32-NEXT: vsseg7e64.v v21, (a0)
|
|
; RV32-NEXT: vl1re64.v v10, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re64.v v11, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re64.v v12, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re64.v v13, (a6)
|
|
; RV32-NEXT: add a6, a3, a2
|
|
; RV32-NEXT: vl1re64.v v18, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re64.v v19, (a6)
|
|
; RV32-NEXT: vl1re64.v v16, (a1)
|
|
; RV32-NEXT: vl1re64.v v8, (a4)
|
|
; RV32-NEXT: vl1re64.v v17, (a3)
|
|
; RV32-NEXT: vl1re64.v v9, (a7)
|
|
; RV32-NEXT: csrr a1, vlenb
|
|
; RV32-NEXT: li a3, 14
|
|
; RV32-NEXT: mul a1, a1, a3
|
|
; RV32-NEXT: add a1, sp, a1
|
|
; RV32-NEXT: addi a1, a1, 64
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re64.v v20, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: vl1re64.v v21, (a6)
|
|
; RV32-NEXT: add a6, a6, a2
|
|
; RV32-NEXT: slli a2, a2, 3
|
|
; RV32-NEXT: add a2, a1, a2
|
|
; RV32-NEXT: add a5, a1, a5
|
|
; RV32-NEXT: vl1re64.v v22, (a6)
|
|
; RV32-NEXT: vl1re64.v v23, (a0)
|
|
; RV32-NEXT: vs2r.v v12, (a5)
|
|
; RV32-NEXT: vs4r.v v8, (a2)
|
|
; RV32-NEXT: vs8r.v v16, (a1)
|
|
; RV32-NEXT: vl8re64.v v16, (a2)
|
|
; RV32-NEXT: vl8re64.v v8, (a1)
|
|
; RV32-NEXT: addi sp, s0, -80
|
|
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
|
|
; RV32-NEXT: addi sp, sp, 80
|
|
; RV32-NEXT: ret
|
|
;
|
|
; RV64-LABEL: vector_interleave_nxv14i64_nxv2i64:
|
|
; RV64: # %bb.0:
|
|
; RV64-NEXT: addi sp, sp, -80
|
|
; RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
|
|
; RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
|
|
; RV64-NEXT: addi s0, sp, 80
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a0, a0, 5
|
|
; RV64-NEXT: sub sp, sp, a0
|
|
; RV64-NEXT: andi sp, sp, -64
|
|
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; RV64-NEXT: vmv2r.v v26, v20
|
|
; RV64-NEXT: vmv2r.v v24, v16
|
|
; RV64-NEXT: vmv2r.v v22, v12
|
|
; RV64-NEXT: vmv2r.v v20, v8
|
|
; RV64-NEXT: addi a1, sp, 64
|
|
; RV64-NEXT: csrr a0, vlenb
|
|
; RV64-NEXT: slli a2, a0, 3
|
|
; RV64-NEXT: sub a0, a2, a0
|
|
; RV64-NEXT: add a0, sp, a0
|
|
; RV64-NEXT: addi a0, a0, 64
|
|
; RV64-NEXT: csrr a2, vlenb
|
|
; RV64-NEXT: add a3, a1, a2
|
|
; RV64-NEXT: add a4, a0, a2
|
|
; RV64-NEXT: slli a5, a2, 2
|
|
; RV64-NEXT: slli a6, a2, 4
|
|
; RV64-NEXT: add a7, a4, a2
|
|
; RV64-NEXT: sub a5, a6, a5
|
|
; RV64-NEXT: vmv1r.v v1, v20
|
|
; RV64-NEXT: vmv1r.v v3, v22
|
|
; RV64-NEXT: vmv1r.v v5, v24
|
|
; RV64-NEXT: vmv1r.v v7, v26
|
|
; RV64-NEXT: add a6, a7, a2
|
|
; RV64-NEXT: vmv1r.v v2, v10
|
|
; RV64-NEXT: vmv1r.v v4, v14
|
|
; RV64-NEXT: vmv1r.v v6, v18
|
|
; RV64-NEXT: vsseg7e64.v v1, (a1)
|
|
; RV64-NEXT: vmv1r.v v22, v11
|
|
; RV64-NEXT: vmv1r.v v24, v15
|
|
; RV64-NEXT: vmv1r.v v26, v19
|
|
; RV64-NEXT: vsseg7e64.v v21, (a0)
|
|
; RV64-NEXT: vl1re64.v v10, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re64.v v11, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re64.v v12, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re64.v v13, (a6)
|
|
; RV64-NEXT: add a6, a3, a2
|
|
; RV64-NEXT: vl1re64.v v18, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re64.v v19, (a6)
|
|
; RV64-NEXT: vl1re64.v v16, (a1)
|
|
; RV64-NEXT: vl1re64.v v8, (a4)
|
|
; RV64-NEXT: vl1re64.v v17, (a3)
|
|
; RV64-NEXT: vl1re64.v v9, (a7)
|
|
; RV64-NEXT: csrr a1, vlenb
|
|
; RV64-NEXT: li a3, 14
|
|
; RV64-NEXT: mul a1, a1, a3
|
|
; RV64-NEXT: add a1, sp, a1
|
|
; RV64-NEXT: addi a1, a1, 64
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re64.v v20, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: vl1re64.v v21, (a6)
|
|
; RV64-NEXT: add a6, a6, a2
|
|
; RV64-NEXT: slli a2, a2, 3
|
|
; RV64-NEXT: add a2, a1, a2
|
|
; RV64-NEXT: add a5, a1, a5
|
|
; RV64-NEXT: vl1re64.v v22, (a6)
|
|
; RV64-NEXT: vl1re64.v v23, (a0)
|
|
; RV64-NEXT: vs2r.v v12, (a5)
|
|
; RV64-NEXT: vs4r.v v8, (a2)
|
|
; RV64-NEXT: vs8r.v v16, (a1)
|
|
; RV64-NEXT: vl8re64.v v16, (a2)
|
|
; RV64-NEXT: vl8re64.v v8, (a1)
|
|
; RV64-NEXT: addi sp, s0, -80
|
|
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
|
|
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
|
|
; RV64-NEXT: addi sp, sp, 80
|
|
; RV64-NEXT: ret
|
|
;
|
|
; ZVBB-RV32-LABEL: vector_interleave_nxv14i64_nxv2i64:
|
|
; ZVBB-RV32: # %bb.0:
|
|
; ZVBB-RV32-NEXT: addi sp, sp, -80
|
|
; ZVBB-RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
|
|
; ZVBB-RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
|
|
; ZVBB-RV32-NEXT: addi s0, sp, 80
|
|
; ZVBB-RV32-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV32-NEXT: slli a0, a0, 5
|
|
; ZVBB-RV32-NEXT: sub sp, sp, a0
|
|
; ZVBB-RV32-NEXT: andi sp, sp, -64
|
|
; ZVBB-RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; ZVBB-RV32-NEXT: vmv2r.v v26, v20
|
|
; ZVBB-RV32-NEXT: vmv2r.v v24, v16
|
|
; ZVBB-RV32-NEXT: vmv2r.v v22, v12
|
|
; ZVBB-RV32-NEXT: vmv2r.v v20, v8
|
|
; ZVBB-RV32-NEXT: addi a1, sp, 64
|
|
; ZVBB-RV32-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV32-NEXT: slli a2, a0, 3
|
|
; ZVBB-RV32-NEXT: sub a0, a2, a0
|
|
; ZVBB-RV32-NEXT: add a0, sp, a0
|
|
; ZVBB-RV32-NEXT: addi a0, a0, 64
|
|
; ZVBB-RV32-NEXT: csrr a2, vlenb
|
|
; ZVBB-RV32-NEXT: add a3, a1, a2
|
|
; ZVBB-RV32-NEXT: add a4, a0, a2
|
|
; ZVBB-RV32-NEXT: slli a5, a2, 2
|
|
; ZVBB-RV32-NEXT: slli a6, a2, 4
|
|
; ZVBB-RV32-NEXT: add a7, a4, a2
|
|
; ZVBB-RV32-NEXT: sub a5, a6, a5
|
|
; ZVBB-RV32-NEXT: vmv1r.v v1, v20
|
|
; ZVBB-RV32-NEXT: vmv1r.v v3, v22
|
|
; ZVBB-RV32-NEXT: vmv1r.v v5, v24
|
|
; ZVBB-RV32-NEXT: vmv1r.v v7, v26
|
|
; ZVBB-RV32-NEXT: add a6, a7, a2
|
|
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
|
|
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
|
|
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
|
|
; ZVBB-RV32-NEXT: vsseg7e64.v v1, (a1)
|
|
; ZVBB-RV32-NEXT: vmv1r.v v22, v11
|
|
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
|
|
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
|
|
; ZVBB-RV32-NEXT: vsseg7e64.v v21, (a0)
|
|
; ZVBB-RV32-NEXT: vl1re64.v v10, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re64.v v11, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re64.v v12, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re64.v v13, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a3, a2
|
|
; ZVBB-RV32-NEXT: vl1re64.v v18, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re64.v v19, (a6)
|
|
; ZVBB-RV32-NEXT: vl1re64.v v16, (a1)
|
|
; ZVBB-RV32-NEXT: vl1re64.v v8, (a4)
|
|
; ZVBB-RV32-NEXT: vl1re64.v v17, (a3)
|
|
; ZVBB-RV32-NEXT: vl1re64.v v9, (a7)
|
|
; ZVBB-RV32-NEXT: csrr a1, vlenb
|
|
; ZVBB-RV32-NEXT: li a3, 14
|
|
; ZVBB-RV32-NEXT: mul a1, a1, a3
|
|
; ZVBB-RV32-NEXT: add a1, sp, a1
|
|
; ZVBB-RV32-NEXT: addi a1, a1, 64
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re64.v v20, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: vl1re64.v v21, (a6)
|
|
; ZVBB-RV32-NEXT: add a6, a6, a2
|
|
; ZVBB-RV32-NEXT: slli a2, a2, 3
|
|
; ZVBB-RV32-NEXT: add a2, a1, a2
|
|
; ZVBB-RV32-NEXT: add a5, a1, a5
|
|
; ZVBB-RV32-NEXT: vl1re64.v v22, (a6)
|
|
; ZVBB-RV32-NEXT: vl1re64.v v23, (a0)
|
|
; ZVBB-RV32-NEXT: vs2r.v v12, (a5)
|
|
; ZVBB-RV32-NEXT: vs4r.v v8, (a2)
|
|
; ZVBB-RV32-NEXT: vs8r.v v16, (a1)
|
|
; ZVBB-RV32-NEXT: vl8re64.v v16, (a2)
|
|
; ZVBB-RV32-NEXT: vl8re64.v v8, (a1)
|
|
; ZVBB-RV32-NEXT: addi sp, s0, -80
|
|
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
|
|
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
|
|
; ZVBB-RV32-NEXT: addi sp, sp, 80
|
|
; ZVBB-RV32-NEXT: ret
|
|
;
|
|
; ZVBB-RV64-LABEL: vector_interleave_nxv14i64_nxv2i64:
|
|
; ZVBB-RV64: # %bb.0:
|
|
; ZVBB-RV64-NEXT: addi sp, sp, -80
|
|
; ZVBB-RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
|
|
; ZVBB-RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
|
|
; ZVBB-RV64-NEXT: addi s0, sp, 80
|
|
; ZVBB-RV64-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV64-NEXT: slli a0, a0, 5
|
|
; ZVBB-RV64-NEXT: sub sp, sp, a0
|
|
; ZVBB-RV64-NEXT: andi sp, sp, -64
|
|
; ZVBB-RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
|
|
; ZVBB-RV64-NEXT: vmv2r.v v26, v20
|
|
; ZVBB-RV64-NEXT: vmv2r.v v24, v16
|
|
; ZVBB-RV64-NEXT: vmv2r.v v22, v12
|
|
; ZVBB-RV64-NEXT: vmv2r.v v20, v8
|
|
; ZVBB-RV64-NEXT: addi a1, sp, 64
|
|
; ZVBB-RV64-NEXT: csrr a0, vlenb
|
|
; ZVBB-RV64-NEXT: slli a2, a0, 3
|
|
; ZVBB-RV64-NEXT: sub a0, a2, a0
|
|
; ZVBB-RV64-NEXT: add a0, sp, a0
|
|
; ZVBB-RV64-NEXT: addi a0, a0, 64
|
|
; ZVBB-RV64-NEXT: csrr a2, vlenb
|
|
; ZVBB-RV64-NEXT: add a3, a1, a2
|
|
; ZVBB-RV64-NEXT: add a4, a0, a2
|
|
; ZVBB-RV64-NEXT: slli a5, a2, 2
|
|
; ZVBB-RV64-NEXT: slli a6, a2, 4
|
|
; ZVBB-RV64-NEXT: add a7, a4, a2
|
|
; ZVBB-RV64-NEXT: sub a5, a6, a5
|
|
; ZVBB-RV64-NEXT: vmv1r.v v1, v20
|
|
; ZVBB-RV64-NEXT: vmv1r.v v3, v22
|
|
; ZVBB-RV64-NEXT: vmv1r.v v5, v24
|
|
; ZVBB-RV64-NEXT: vmv1r.v v7, v26
|
|
; ZVBB-RV64-NEXT: add a6, a7, a2
|
|
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
|
|
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
|
|
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
|
|
; ZVBB-RV64-NEXT: vsseg7e64.v v1, (a1)
|
|
; ZVBB-RV64-NEXT: vmv1r.v v22, v11
|
|
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
|
|
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
|
|
; ZVBB-RV64-NEXT: vsseg7e64.v v21, (a0)
|
|
; ZVBB-RV64-NEXT: vl1re64.v v10, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re64.v v11, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re64.v v12, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re64.v v13, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a3, a2
|
|
; ZVBB-RV64-NEXT: vl1re64.v v18, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re64.v v19, (a6)
|
|
; ZVBB-RV64-NEXT: vl1re64.v v16, (a1)
|
|
; ZVBB-RV64-NEXT: vl1re64.v v8, (a4)
|
|
; ZVBB-RV64-NEXT: vl1re64.v v17, (a3)
|
|
; ZVBB-RV64-NEXT: vl1re64.v v9, (a7)
|
|
; ZVBB-RV64-NEXT: csrr a1, vlenb
|
|
; ZVBB-RV64-NEXT: li a3, 14
|
|
; ZVBB-RV64-NEXT: mul a1, a1, a3
|
|
; ZVBB-RV64-NEXT: add a1, sp, a1
|
|
; ZVBB-RV64-NEXT: addi a1, a1, 64
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re64.v v20, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: vl1re64.v v21, (a6)
|
|
; ZVBB-RV64-NEXT: add a6, a6, a2
|
|
; ZVBB-RV64-NEXT: slli a2, a2, 3
|
|
; ZVBB-RV64-NEXT: add a2, a1, a2
|
|
; ZVBB-RV64-NEXT: add a5, a1, a5
|
|
; ZVBB-RV64-NEXT: vl1re64.v v22, (a6)
|
|
; ZVBB-RV64-NEXT: vl1re64.v v23, (a0)
|
|
; ZVBB-RV64-NEXT: vs2r.v v12, (a5)
|
|
; ZVBB-RV64-NEXT: vs4r.v v8, (a2)
|
|
; ZVBB-RV64-NEXT: vs8r.v v16, (a1)
|
|
; ZVBB-RV64-NEXT: vl8re64.v v16, (a2)
|
|
; ZVBB-RV64-NEXT: vl8re64.v v8, (a1)
|
|
; ZVBB-RV64-NEXT: addi sp, s0, -80
|
|
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
|
|
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
|
|
; ZVBB-RV64-NEXT: addi sp, sp, 80
|
|
; ZVBB-RV64-NEXT: ret
|
|
%res = call <vscale x 14 x i64> @llvm.vector.interleave7.nxv14i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e, <vscale x 2 x i64> %f, <vscale x 2 x i64> %g)
|
|
ret <vscale x 14 x i64> %res
|
|
}
|