58a88001f3
This fixes the handling of subregister extract copies. This will allow AMDGPU to remove its implementation of shouldRewriteCopySrc, which exists as a 10 year old workaround to this bug. peephole-opt-fold-reg-sequence-subreg.mir will show the expected improvement once the custom implementation is removed. The copy coalescing processing here is overly abstracted from what's actually happening. Previously when visiting coalescable copy-like instructions, we would parse the sources one at a time and then pass the def of the root instruction into findNextSource. This means that the first thing the new ValueTracker constructed would do is getVRegDef to find the instruction we are currently processing. This adds an unnecessary step, placing a useless entry in the RewriteMap, and required skipping the no-op case where getNewSource would return the original source operand. This was a problem since in the case of a subregister extract, shouldRewriteCopySource would always say that it is useful to rewrite and the use-def chain walk would abort, returning the original operand. Move the process to start looking at the source operand to begin with. This does not fix the confused handling in the uncoalescable copy case which is proving to be more difficult. Some currently handled cases have multiple defs from a single source, and other handled cases have 0 input operands. It would be simpler if this was implemented with isCopyLikeInstr, rather than guessing at the operand structure as it does now. There are some improvements and some regressions. The regressions appear to be downstream issues for the most part. One of the uglier regressions is in PPC, where a sequence of insert_subrgs is used to build registers. I opened #125502 to use reg_sequence instead, which may help. The worst regression is an absurd SPARC testcase using a <251 x fp128>, which uses a very long chain of insert_subregs. We need improved subregister handling locally in PeepholeOptimizer, and other pasess like MachineCSE to fix some of the other regressions. We should handle subregister composes and folding more indexes into insert_subreg and reg_sequence.
530 lines
16 KiB
LLVM
530 lines
16 KiB
LLVM
; RUN: llc < %s -mtriple=ve | FileCheck %s
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;;; Test ‘select’ instruction
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;;;
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;;; Syntax:
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;;; <result> = select [fast-math flags] selty <cond>, <ty> <val1>, <ty> <val2>
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;;; ; yields ty
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;;;
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;;; selty is either i1 or {<N x i1>}
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;;;
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;;; Overview:
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;;; The ‘select’ instruction is used to choose one value based on a condition,
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;;; without IR-level branching.
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;;;
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;;; Arguments:
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;;; The ‘select’ instruction requires an ‘i1’ value or a vector of ‘i1’ values
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;;; indicating the condition, and two values of the same first class type.
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;;;
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;;; The optional fast-math flags marker indicates that the select has one or
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;;; more fast-math flags. These are optimization hints to enable otherwise
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;;; unsafe floating-point optimizations. Fast-math flags are only valid for
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;;; selects that return a floating-point scalar or vector type, or an array
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;;; (nested to any depth) of floating-point scalar or vector types.
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;;;
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;;; Semantics:
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;;; If the condition is an i1 and it evaluates to 1, the instruction returns
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;;; the first value argument; otherwise, it returns the second value argument.
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;;;
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;;; If the condition is a vector of i1, then the value arguments must be
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;;; vectors of the same size, and the selection is done element by element.
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;;;
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;;; If the condition is an i1 and the value arguments are vectors of the same
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;;; size, then an entire vector is selected.
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;;;
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;;; Example:
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;;; %X = select i1 true, i8 17, i8 42 ; yields i8:17
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;;;
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;;; Note:
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;;; We test only i1/i8/u8/i16/u16/i32/u32/i64/u64/i128/u128/float/double/fp128
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @select_i1_var(i1 zeroext %0, i1 zeroext %1, i1 zeroext %2) {
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; CHECK-LABEL: select_i1_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = select i1 %0, i1 %1, i1 %2
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ret i1 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i8 @select_i8_var(i1 zeroext %0, i8 signext %1, i8 signext %2) {
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; CHECK-LABEL: select_i8_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = select i1 %0, i8 %1, i8 %2
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ret i8 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i8 @select_u8_var(i1 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
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; CHECK-LABEL: select_u8_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = select i1 %0, i8 %1, i8 %2
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ret i8 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i16 @select_i16_var(i1 zeroext %0, i16 signext %1, i16 signext %2) {
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; CHECK-LABEL: select_i16_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = select i1 %0, i16 %1, i16 %2
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ret i16 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i16 @select_u16_var(i1 zeroext %0, i16 zeroext %1, i16 zeroext %2) {
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; CHECK-LABEL: select_u16_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = select i1 %0, i16 %1, i16 %2
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ret i16 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @select_i32_var(i1 zeroext %0, i32 signext %1, i32 signext %2) {
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; CHECK-LABEL: select_i32_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = select i1 %0, i32 %1, i32 %2
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ret i32 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i32 @select_u32_var(i1 zeroext %0, i32 zeroext %1, i32 zeroext %2) {
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; CHECK-LABEL: select_u32_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = select i1 %0, i32 %1, i32 %2
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ret i32 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @select_i64_var(i1 zeroext %0, i64 %1, i64 %2) {
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; CHECK-LABEL: select_i64_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: or %s0, 0, %s2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = select i1 %0, i64 %1, i64 %2
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ret i64 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @select_u64_var(i1 zeroext %0, i64 %1, i64 %2) {
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; CHECK-LABEL: select_u64_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: or %s0, 0, %s2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = select i1 %0, i64 %1, i64 %2
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ret i64 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @select_i128_var(i1 zeroext %0, i128 %1, i128 %2) {
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; CHECK-LABEL: select_i128_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s3, %s1, %s0
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; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
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; CHECK-NEXT: or %s0, 0, %s3
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; CHECK-NEXT: or %s1, 0, %s4
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = select i1 %0, i128 %1, i128 %2
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ret i128 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @select_u128_var(i1 zeroext %0, i128 %1, i128 %2) {
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; CHECK-LABEL: select_u128_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s3, %s1, %s0
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; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
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; CHECK-NEXT: or %s0, 0, %s3
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; CHECK-NEXT: or %s1, 0, %s4
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = select i1 %0, i128 %1, i128 %2
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ret i128 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define float @select_float_var(i1 zeroext %0, float %1, float %2) {
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; CHECK-LABEL: select_float_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: or %s0, 0, %s2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = select fast i1 %0, float %1, float %2
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ret float %4
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}
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; Function Attrs: norecurse nounwind readnone
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define double @select_double_var(i1 zeroext %0, double %1, double %2) {
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; CHECK-LABEL: select_double_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: or %s0, 0, %s2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = select fast i1 %0, double %1, double %2
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ret double %4
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}
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; Function Attrs: norecurse nounwind readnone
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define fp128 @select_quad_var(i1 zeroext %0, fp128 %1, fp128 %2) {
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; CHECK-LABEL: select_quad_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
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; CHECK-NEXT: cmov.w.ne %s5, %s3, %s0
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; CHECK-NEXT: or %s0, 0, %s4
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; CHECK-NEXT: or %s1, 0, %s5
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = select fast i1 %0, fp128 %1, fp128 %2
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ret fp128 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @select_i1_mimm(i1 zeroext %0, i1 zeroext %1) {
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; CHECK-LABEL: select_i1_mimm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: or %s0, %s0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = or i1 %0, %1
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ret i1 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i8 @select_i8_mimm(i1 zeroext %0, i8 signext %1) {
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; CHECK-LABEL: select_i8_mimm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s1, (57)1, %s0
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; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = select i1 %0, i8 -128, i8 %1
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ret i8 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i8 @select_u8_mimm(i1 zeroext %0, i8 zeroext %1) {
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; CHECK-LABEL: select_u8_mimm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s1, (57)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = select i1 %0, i8 127, i8 %1
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ret i8 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i16 @select_i16_mimm(i1 zeroext %0, i16 signext %1) {
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; CHECK-LABEL: select_i16_mimm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s1, (49)1, %s0
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; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = select i1 %0, i16 -32768, i16 %1
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ret i16 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i16 @select_u16_mimm(i1 zeroext %0, i16 zeroext %1) {
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; CHECK-LABEL: select_u16_mimm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s1, (49)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = select i1 %0, i16 32767, i16 %1
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ret i16 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @select_i32_mimm(i1 zeroext %0, i32 signext %1) {
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; CHECK-LABEL: select_i32_mimm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
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; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = select i1 %0, i32 65535, i32 %1
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ret i32 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i32 @select_u32_mimm(i1 zeroext %0, i32 zeroext %1) {
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; CHECK-LABEL: select_u32_mimm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = select i1 %0, i32 65535, i32 %1
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ret i32 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @select_i64_mimm(i1 zeroext %0, i64 %1) {
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; CHECK-LABEL: select_i64_mimm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = select i1 %0, i64 65535, i64 %1
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ret i64 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @select_u64_mimm(i1 zeroext %0, i64 %1) {
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; CHECK-LABEL: select_u64_mimm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = select i1 %0, i64 65535, i64 %1
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ret i64 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @select_i128_mimm(i1 zeroext %0, i128 %1) {
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; CHECK-LABEL: select_i128_mimm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
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; CHECK-NEXT: cmov.w.ne %s2, (0)1, %s0
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: or %s1, 0, %s2
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = select i1 %0, i128 65535, i128 %1
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ret i128 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @select_u128_mimm(i1 zeroext %0, i128 %1) {
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; CHECK-LABEL: select_u128_mimm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
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; CHECK-NEXT: cmov.w.ne %s2, (0)1, %s0
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: or %s1, 0, %s2
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = select i1 %0, i128 65535, i128 %1
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ret i128 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define float @select_float_mimm(i1 zeroext %0, float %1) {
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; CHECK-LABEL: select_float_mimm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s1, (2)1, %s0
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = select i1 %0, float -2.000000e+00, float %1
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ret float %3
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}
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; Function Attrs: norecurse nounwind readnone
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define double @select_double_mimm(i1 zeroext %0, double %1) {
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; CHECK-LABEL: select_double_mimm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmov.w.ne %s1, (2)1, %s0
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = select fast i1 %0, double -2.000000e+00, double %1
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ret double %3
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}
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; Function Attrs: norecurse nounwind readnone
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define fp128 @select_quad_mimm(i1 zeroext %0, fp128 %1) {
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; CHECK-LABEL: select_quad_mimm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, .LCPI{{[0-9]+}}_0@lo
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lea.sl %s1, .LCPI{{[0-9]+}}_0@hi(, %s1)
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; CHECK-NEXT: ld %s4, 8(, %s1)
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; CHECK-NEXT: ld %s1, (, %s1)
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; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0
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; CHECK-NEXT: cmov.w.ne %s3, %s1, %s0
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; CHECK-NEXT: or %s0, 0, %s2
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; CHECK-NEXT: or %s1, 0, %s3
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = select fast i1 %0, fp128 0xL0000000000000000C000000000000000, fp128 %1
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ret fp128 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @select_mimm_i1(i1 zeroext %0, i1 zeroext %1) {
|
||
; CHECK-LABEL: select_mimm_i1:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: xor %s0, 1, %s0
|
||
; CHECK-NEXT: or %s0, %s0, %s1
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%3 = xor i1 %0, true
|
||
%4 = or i1 %3, %1
|
||
ret i1 %4
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define signext i8 @select_mimm_i8(i1 zeroext %0, i8 signext %1) {
|
||
; CHECK-LABEL: select_mimm_i8:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: cmov.w.eq %s1, (57)1, %s0
|
||
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%3 = select i1 %0, i8 %1, i8 -128
|
||
ret i8 %3
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define zeroext i8 @select_mimm_u8(i1 zeroext %0, i8 zeroext %1) {
|
||
; CHECK-LABEL: select_mimm_u8:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: cmov.w.eq %s1, (57)0, %s0
|
||
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%3 = select i1 %0, i8 %1, i8 127
|
||
ret i8 %3
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define signext i16 @select_mimm_i16(i1 zeroext %0, i16 signext %1) {
|
||
; CHECK-LABEL: select_mimm_i16:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: cmov.w.eq %s1, (49)1, %s0
|
||
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%3 = select i1 %0, i16 %1, i16 -32768
|
||
ret i16 %3
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define zeroext i16 @select_mimm_u16(i1 zeroext %0, i16 zeroext %1) {
|
||
; CHECK-LABEL: select_mimm_u16:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: cmov.w.eq %s1, (49)0, %s0
|
||
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%3 = select i1 %0, i16 %1, i16 32767
|
||
ret i16 %3
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define signext i32 @select_mimm_i32(i1 zeroext %0, i32 signext %1) {
|
||
; CHECK-LABEL: select_mimm_i32:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
|
||
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%3 = select i1 %0, i32 %1, i32 65535
|
||
ret i32 %3
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define zeroext i32 @select_mimm_u32(i1 zeroext %0, i32 zeroext %1) {
|
||
; CHECK-LABEL: select_mimm_u32:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
|
||
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%3 = select i1 %0, i32 %1, i32 65535
|
||
ret i32 %3
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define i64 @select_mimm_i64(i1 zeroext %0, i64 %1) {
|
||
; CHECK-LABEL: select_mimm_i64:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
|
||
; CHECK-NEXT: or %s0, 0, %s1
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%3 = select i1 %0, i64 %1, i64 65535
|
||
ret i64 %3
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define i64 @select_mimm_u64(i1 zeroext %0, i64 %1) {
|
||
; CHECK-LABEL: select_mimm_u64:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
|
||
; CHECK-NEXT: or %s0, 0, %s1
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%3 = select i1 %0, i64 %1, i64 65535
|
||
ret i64 %3
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define i128 @select_mimm_i128(i1 zeroext %0, i128 %1) {
|
||
; CHECK-LABEL: select_mimm_i128:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
|
||
; CHECK-NEXT: cmov.w.eq %s2, (0)1, %s0
|
||
; CHECK-NEXT: or %s0, 0, %s1
|
||
; CHECK-NEXT: or %s1, 0, %s2
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%3 = select i1 %0, i128 %1, i128 65535
|
||
ret i128 %3
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define i128 @select_mimm_u128(i1 zeroext %0, i128 %1) {
|
||
; CHECK-LABEL: select_mimm_u128:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
|
||
; CHECK-NEXT: cmov.w.eq %s2, (0)1, %s0
|
||
; CHECK-NEXT: or %s0, 0, %s1
|
||
; CHECK-NEXT: or %s1, 0, %s2
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%3 = select i1 %0, i128 %1, i128 65535
|
||
ret i128 %3
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define float @select_mimm_float(i1 zeroext %0, float %1) {
|
||
; CHECK-LABEL: select_mimm_float:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: cmov.w.eq %s1, (2)1, %s0
|
||
; CHECK-NEXT: or %s0, 0, %s1
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%3 = select i1 %0, float %1, float -2.000000e+00
|
||
ret float %3
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define double @select_mimm_double(i1 zeroext %0, double %1) {
|
||
; CHECK-LABEL: select_mimm_double:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: cmov.w.eq %s1, (2)1, %s0
|
||
; CHECK-NEXT: or %s0, 0, %s1
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%3 = select fast i1 %0, double %1, double -2.000000e+00
|
||
ret double %3
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define fp128 @select_mimm_quad(i1 zeroext %0, fp128 %1) {
|
||
; CHECK-LABEL: select_mimm_quad:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: lea %s1, .LCPI{{[0-9]+}}_0@lo
|
||
; CHECK-NEXT: and %s1, %s1, (32)0
|
||
; CHECK-NEXT: lea.sl %s1, .LCPI{{[0-9]+}}_0@hi(, %s1)
|
||
; CHECK-NEXT: ld %s4, 8(, %s1)
|
||
; CHECK-NEXT: ld %s5, (, %s1)
|
||
; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
|
||
; CHECK-NEXT: cmov.w.ne %s5, %s3, %s0
|
||
; CHECK-NEXT: or %s0, 0, %s4
|
||
; CHECK-NEXT: or %s1, 0, %s5
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%3 = select fast i1 %0, fp128 %1, fp128 0xL0000000000000000C000000000000000
|
||
ret fp128 %3
|
||
}
|