32c4493d5f
Follow-up as discussed when using VPInstruction::ResumePhi for all resume values (#112147). This patch explicitly adds incoming values for each predecessor in VPlan. This simplifies codegen and allows transformations adjusting the predecessors of blocks with NFC modulo incoming block order in phis.
77 lines
3.9 KiB
LLVM
77 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=loop-vectorize -force-vector-width=4 -S %s | FileCheck %s
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define void @test(ptr %A, i32 %x) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
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; CHECK: vector.scevcheck:
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; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[X:%.*]], 1
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; CHECK-NEXT: br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 0
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; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[OFFSET_IDX]] to i32
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; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 0
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; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
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; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
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; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[TMP5]]
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i32 0
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP7]], align 4
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; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP1]] to i64
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP8]]
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; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i32 0
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; CHECK-NEXT: store <4 x float> [[WIDE_LOAD]], ptr [[TMP10]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[OFFSET_IDX]], 4
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; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], undef
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; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ undef, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[T_IV_NEXT:%.*]] = trunc i64 [[IV_NEXT]] to i32
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; CHECK-NEXT: [[MUL_IV_NEXT:%.*]] = mul i32 [[T_IV_NEXT]], [[X]]
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; CHECK-NEXT: [[IDX_1:%.*]] = zext i32 [[MUL_IV_NEXT]] to i64
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; CHECK-NEXT: [[ARRAYIDX1215:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IDX_1]]
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; CHECK-NEXT: [[LV:%.*]] = load float, ptr [[ARRAYIDX1215]], align 4
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; CHECK-NEXT: [[T_IV:%.*]] = trunc i64 [[IV]] to i32
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; CHECK-NEXT: [[MUL_IV:%.*]] = mul i32 [[T_IV]], [[X]]
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; CHECK-NEXT: [[IDX_2:%.*]] = zext i32 [[MUL_IV]] to i64
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; CHECK-NEXT: [[ARRAYIDX1209:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IDX_2]]
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; CHECK-NEXT: store float [[LV]], ptr [[ARRAYIDX1209]], align 4
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; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], undef
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; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop: ; preds = %loop, %entry
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%iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]
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%iv.next = add nuw nsw i64 %iv, 1
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%t.iv.next = trunc i64 %iv.next to i32
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%mul.iv.next = mul i32 %t.iv.next, %x
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%idx.1 = zext i32 %mul.iv.next to i64
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%arrayidx1215 = getelementptr inbounds float, ptr %A, i64 %idx.1
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%lv = load float, ptr %arrayidx1215, align 4
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%t.iv = trunc i64 %iv to i32
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%mul.iv = mul i32 %t.iv, %x
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%idx.2 = zext i32 %mul.iv to i64
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%arrayidx1209 = getelementptr inbounds float, ptr %A, i64 %idx.2
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store float %lv, ptr %arrayidx1209, align 4
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%ec = icmp eq i64 %iv.next, undef
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br i1 %ec, label %exit, label %loop
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exit: ; preds = %loop
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ret void
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}
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