2238dcc393
This is an ongoing series of commits that are reformatting our Python code. Reformatting is done with `black` (23.1.0). If you end up having problems merging this commit because you have made changes to a python file, the best way to handle that is to run `git checkout --ours <yourfile>` and then reformat it with black. RFC: https://discourse.llvm.org/t/rfc-document-and-standardize-python-code-style Differential revision: https://reviews.llvm.org/D151460
77 lines
3.3 KiB
Python
77 lines
3.3 KiB
Python
"""
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Use lldb Python API to disassemble raw machine code bytes
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"""
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import re
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import lldb
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from lldbsuite.test.decorators import *
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from lldbsuite.test.lldbtest import *
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from lldbsuite.test import lldbutil
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class DisassembleRawDataTestCase(TestBase):
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@no_debug_info_test
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@skipIfRemote
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def test_disassemble_raw_data(self):
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"""Test disassembling raw bytes with the API."""
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# Create a target from the debugger.
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arch = self.getArchitecture()
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if re.match("mips*el", arch):
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target = self.dbg.CreateTargetWithFileAndTargetTriple("", "mipsel")
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raw_bytes = bytearray([0x21, 0xF0, 0xA0, 0x03])
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elif re.match("mips", arch):
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target = self.dbg.CreateTargetWithFileAndTargetTriple("", "mips")
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raw_bytes = bytearray([0x03, 0xA0, 0xF0, 0x21])
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elif re.match("powerpc64le", arch):
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target = self.dbg.CreateTargetWithFileAndTargetTriple("", "powerpc64le")
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raw_bytes = bytearray([0x00, 0x00, 0x80, 0x38])
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elif arch in ("aarch64", "arm64"):
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target = self.dbg.CreateTargetWithFileAndTargetTriple("", "aarch64")
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raw_bytes = bytearray([0x60, 0x0C, 0x80, 0x52])
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elif arch == "arm":
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target = self.dbg.CreateTargetWithFileAndTargetTriple("", "arm")
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raw_bytes = bytearray([0x63, 0x30, 0xA0, 0xE3])
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else:
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target = self.dbg.CreateTargetWithFileAndTargetTriple("", "x86_64")
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raw_bytes = bytearray([0x48, 0x89, 0xE5])
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self.assertTrue(target, VALID_TARGET)
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insts = target.GetInstructions(lldb.SBAddress(0, target), raw_bytes)
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inst = insts.GetInstructionAtIndex(0)
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if self.TraceOn():
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print()
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print("Raw bytes: ", [hex(x) for x in raw_bytes])
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print("Disassembled%s" % str(inst))
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if re.match("mips", arch):
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self.assertEqual(inst.GetMnemonic(target), "move")
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self.assertEqual(inst.GetOperands(target), "$" + "fp, " + "$" + "sp")
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self.assertEqual(
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inst.GetControlFlowKind(target), lldb.eInstructionControlFlowKindUnknown
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)
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elif re.match("powerpc64le", arch):
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self.assertEqual(inst.GetMnemonic(target), "li")
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self.assertEqual(inst.GetOperands(target), "4, 0")
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self.assertEqual(
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inst.GetControlFlowKind(target), lldb.eInstructionControlFlowKindUnknown
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)
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elif arch in ("aarch64", "arm64"):
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self.assertEqual(inst.GetMnemonic(target), "mov")
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self.assertEqual(inst.GetOperands(target), "w0, #0x63")
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self.assertEqual(
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inst.GetControlFlowKind(target), lldb.eInstructionControlFlowKindUnknown
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)
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elif arch == "arm":
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self.assertEqual(inst.GetMnemonic(target), "mov")
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self.assertEqual(inst.GetOperands(target), "r3, #99")
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self.assertEqual(
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inst.GetControlFlowKind(target), lldb.eInstructionControlFlowKindUnknown
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)
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else:
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self.assertEqual(inst.GetMnemonic(target), "movq")
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self.assertEqual(inst.GetOperands(target), "%" + "rsp, " + "%" + "rbp")
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self.assertEqual(
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inst.GetControlFlowKind(target), lldb.eInstructionControlFlowKindOther
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)
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