a21387c654
This seems to have caused incorrect register allocation in some cases, breaking tests in the Zig standard library (PR47278). As discussed on the bug, revert back to green for now. > Record internal state based on register units. This is often more > efficient as there are typically fewer register units to update > compared to iterating over all the aliases of a register. > > Original patch by Matthias Braun, but I've been rebasing and fixing it > for almost 2 years and fixed a few bugs causing intermediate failures > to make this patch independent of the changes in > https://reviews.llvm.org/D52010. This reverts commit66251f7e1d, and follow-ups931a68f26band0671a4c508. It also adjust some test expectations.
132 lines
2.6 KiB
LLVM
132 lines
2.6 KiB
LLVM
; RUN: llc -O0 -fast-isel -verify-machineinstrs -mtriple=arm64-eabi < %s | FileCheck --enable-var-scope %s
|
|
|
|
; Test fptosi
|
|
define i32 @fptosi_wh(half %a) nounwind ssp {
|
|
entry:
|
|
; CHECK-LABEL: fptosi_wh
|
|
; CHECK: fcvt s1, h0
|
|
; CHECK: fcvtzs [[REG:w[0-9]+]], s1
|
|
; CHECK: mov w0, [[REG]]
|
|
%conv = fptosi half %a to i32
|
|
ret i32 %conv
|
|
}
|
|
|
|
; Test fptoui
|
|
define i32 @fptoui_swh(half %a) nounwind ssp {
|
|
entry:
|
|
; CHECK-LABEL: fptoui_swh
|
|
; CHECK: fcvt s1, h0
|
|
; CHECK: fcvtzu [[REG:w[0-9]+]], s1
|
|
; CHECK: mov w0, [[REG]]
|
|
%conv = fptoui half %a to i32
|
|
ret i32 %conv
|
|
}
|
|
|
|
; Test sitofp
|
|
define half @sitofp_hw_i1(i1 %a) nounwind ssp {
|
|
entry:
|
|
; CHECK-LABEL: sitofp_hw_i1
|
|
; CHECK: sbfx w8, w0, #0, #1
|
|
; CHECK: scvtf s0, w8
|
|
; CHECK: fcvt h0, s0
|
|
%conv = sitofp i1 %a to half
|
|
ret half %conv
|
|
}
|
|
|
|
; Test sitofp
|
|
define half @sitofp_hw_i8(i8 %a) nounwind ssp {
|
|
entry:
|
|
; CHECK-LABEL: sitofp_hw_i8
|
|
; CHECK: sxtb w8, w0
|
|
; CHECK: scvtf s0, w8
|
|
; CHECK: fcvt h0, s0
|
|
%conv = sitofp i8 %a to half
|
|
ret half %conv
|
|
}
|
|
|
|
; Test sitofp
|
|
define half @sitofp_hw_i16(i16 %a) nounwind ssp {
|
|
entry:
|
|
; CHECK-LABEL: sitofp_hw_i16
|
|
; CHECK: sxth w8, w0
|
|
; CHECK: scvtf s0, w8
|
|
; CHECK: fcvt h0, s0
|
|
%conv = sitofp i16 %a to half
|
|
ret half %conv
|
|
}
|
|
|
|
; Test sitofp
|
|
define half @sitofp_hw_i32(i32 %a) nounwind ssp {
|
|
entry:
|
|
; CHECK-LABEL: sitofp_hw_i32
|
|
; CHECK: scvtf s0, w0
|
|
; CHECK: fcvt h0, s0
|
|
%conv = sitofp i32 %a to half
|
|
ret half %conv
|
|
}
|
|
|
|
; Test sitofp
|
|
define half @sitofp_hx(i64 %a) nounwind ssp {
|
|
entry:
|
|
; CHECK-LABEL: sitofp_hx
|
|
; CHECK: scvtf s0, x0
|
|
; CHECK: fcvt h0, s0
|
|
%conv = sitofp i64 %a to half
|
|
ret half %conv
|
|
}
|
|
|
|
; Test uitofp
|
|
define half @uitofp_hw_i1(i1 %a) nounwind ssp {
|
|
entry:
|
|
; CHECK-LABEL: uitofp_hw_i1
|
|
; CHECK: and w8, w0, #0x1
|
|
; CHECK: ucvtf s0, w8
|
|
; CHECK: fcvt h0, s0
|
|
%conv = uitofp i1 %a to half
|
|
ret half %conv
|
|
}
|
|
|
|
; Test uitofp
|
|
define half @uitofp_hw_i8(i8 %a) nounwind ssp {
|
|
entry:
|
|
; CHECK-LABEL: uitofp_hw_i8
|
|
; CHECK: and w8, w0, #0xff
|
|
; CHECK: ucvtf s0, w8
|
|
; CHECK: fcvt h0, s0
|
|
%conv = uitofp i8 %a to half
|
|
ret half %conv
|
|
}
|
|
|
|
; Test uitofp
|
|
define half @uitofp_hw_i16(i16 %a) nounwind ssp {
|
|
entry:
|
|
; CHECK-LABEL: uitofp_hw_i16
|
|
; CHECK: and w8, w0, #0xffff
|
|
; CHECK: ucvtf s0, w8
|
|
; CHECK: fcvt h0, s0
|
|
%conv = uitofp i16 %a to half
|
|
ret half %conv
|
|
}
|
|
|
|
; Test uitofp
|
|
define half @uitofp_hw_i32(i32 %a) nounwind ssp {
|
|
entry:
|
|
; CHECK-LABEL: uitofp_hw_i32
|
|
; CHECK: ucvtf s0, w0
|
|
; CHECK: fcvt h0, s0
|
|
%conv = uitofp i32 %a to half
|
|
ret half %conv
|
|
}
|
|
|
|
; Test uitofp
|
|
define half @uitofp_hx(i64 %a) nounwind ssp {
|
|
entry:
|
|
; CHECK-LABEL: uitofp_hx
|
|
; CHECK: ucvtf s0, x0
|
|
; CHECK: fcvt h0, s0
|
|
%conv = uitofp i64 %a to half
|
|
ret half %conv
|
|
}
|
|
|
|
|