a21387c654
This seems to have caused incorrect register allocation in some cases, breaking tests in the Zig standard library (PR47278). As discussed on the bug, revert back to green for now. > Record internal state based on register units. This is often more > efficient as there are typically fewer register units to update > compared to iterating over all the aliases of a register. > > Original patch by Matthias Braun, but I've been rebasing and fixing it > for almost 2 years and fixed a few bugs causing intermediate failures > to make this patch independent of the changes in > https://reviews.llvm.org/D52010. This reverts commit66251f7e1d, and follow-ups931a68f26band0671a4c508. It also adjust some test expectations.
113 lines
3.9 KiB
LLVM
113 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=mips64-unknown-freebsd -O0 -o - %s | FileCheck %s
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; Previously SelectionDAGBuilder would always set alignment to 1 for hidden sret
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; parameters so we were generating ldl+ldr/lwl+lwr to load those values even
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; though we know that they are aligned (since we allocated an aligned frame index)
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declare dso_local void @use_sret(i32, i128, i64) unnamed_addr
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declare dso_local { i32, i128, i64 } @implicit_sret_decl() unnamed_addr
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define internal void @test() unnamed_addr nounwind {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: daddiu $sp, $sp, -48
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; CHECK-NEXT: sd $ra, 40($sp) # 8-byte Folded Spill
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; CHECK-NEXT: daddiu $4, $sp, 8
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; CHECK-NEXT: jal implicit_sret_decl
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; CHECK-NEXT: nop
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; CHECK-NEXT: ld $6, 24($sp)
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; CHECK-NEXT: ld $5, 16($sp)
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; CHECK-NEXT: ld $7, 32($sp)
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; CHECK-NEXT: lw $1, 8($sp)
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; CHECK-NEXT: # implicit-def: $v0_64
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; CHECK-NEXT: move $2, $1
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; CHECK-NEXT: move $4, $2
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; CHECK-NEXT: jal use_sret
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; CHECK-NEXT: nop
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; CHECK-NEXT: ld $ra, 40($sp) # 8-byte Folded Reload
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; CHECK-NEXT: daddiu $sp, $sp, 48
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: nop
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start:
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%0 = call { i32, i128, i64 } @implicit_sret_decl()
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%1 = extractvalue { i32, i128, i64 } %0, 0
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%2 = extractvalue { i32, i128, i64 } %0, 1
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%3 = extractvalue { i32, i128, i64 } %0, 2
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call void @use_sret(i32 %1, i128 %2, i64 %3)
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ret void
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}
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define internal { i32, i128, i64 } @implicit_sret_impl() unnamed_addr nounwind {
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; CHECK-LABEL: implicit_sret_impl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: move $1, $4
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; CHECK-NEXT: daddiu $2, $zero, 20
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; CHECK-NEXT: sd $2, 16($4)
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; CHECK-NEXT: daddiu $2, $zero, 0
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; CHECK-NEXT: sd $zero, 8($4)
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; CHECK-NEXT: daddiu $3, $zero, 30
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; CHECK-NEXT: sd $3, 24($4)
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; CHECK-NEXT: addiu $5, $zero, 10
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; CHECK-NEXT: sw $5, 0($4)
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: nop
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ret { i32, i128, i64 } { i32 10, i128 20, i64 30 }
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}
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declare dso_local { i32, i32, i32, i32, i32, i32 } @implicit_sret_decl2() unnamed_addr
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declare dso_local void @use_sret2(i32, i32, i32) unnamed_addr
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define internal void @test2() unnamed_addr nounwind {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: daddiu $sp, $sp, -32
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; CHECK-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill
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; CHECK-NEXT: daddiu $4, $sp, 0
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; CHECK-NEXT: jal implicit_sret_decl2
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; CHECK-NEXT: nop
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; CHECK-NEXT: lw $1, 20($sp)
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; CHECK-NEXT: lw $2, 12($sp)
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; CHECK-NEXT: lw $3, 4($sp)
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; CHECK-NEXT: # implicit-def: $a0_64
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; CHECK-NEXT: move $4, $3
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; CHECK-NEXT: # implicit-def: $a1_64
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; CHECK-NEXT: move $5, $2
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; CHECK-NEXT: # implicit-def: $a2_64
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; CHECK-NEXT: move $6, $1
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; CHECK-NEXT: jal use_sret2
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; CHECK-NEXT: nop
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; CHECK-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload
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; CHECK-NEXT: daddiu $sp, $sp, 32
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: nop
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start:
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%0 = call { i32, i32, i32, i32, i32, i32 } @implicit_sret_decl2()
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%1 = extractvalue { i32, i32, i32, i32, i32, i32 } %0, 1
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%2 = extractvalue { i32, i32, i32, i32, i32, i32 } %0, 3
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%3 = extractvalue { i32, i32, i32, i32, i32, i32 } %0, 5
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call void @use_sret2(i32 %1, i32 %2, i32 %3)
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ret void
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}
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define internal { i32, i32, i32, i32, i32, i32 } @implicit_sret_impl2() unnamed_addr nounwind {
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; CHECK-LABEL: implicit_sret_impl2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: move $1, $4
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; CHECK-NEXT: addiu $2, $zero, 6
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; CHECK-NEXT: sw $2, 20($4)
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; CHECK-NEXT: addiu $2, $zero, 5
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; CHECK-NEXT: sw $2, 16($4)
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; CHECK-NEXT: addiu $2, $zero, 4
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; CHECK-NEXT: sw $2, 12($4)
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; CHECK-NEXT: addiu $2, $zero, 3
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; CHECK-NEXT: sw $2, 8($4)
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; CHECK-NEXT: addiu $2, $zero, 2
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; CHECK-NEXT: sw $2, 4($4)
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; CHECK-NEXT: addiu $2, $zero, 1
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; CHECK-NEXT: sw $2, 0($4)
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: nop
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ret { i32, i32, i32, i32, i32, i32 } { i32 1, i32 2, i32 3, i32 4, i32 5, i32 6 }
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}
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