015184b79e
Summary: It seems it's main effect is to create addition copies when values are inr register that do not support this trick, which increase register pressure and makes the code bigger. The main noteworthy regression I was able to observe was pattern of the type (setcc (trunc (and X, C)), 0) where C is such as it would benefit from the hi register trick. To prevent this, a new pattern is added to materialize such pattern using a 32 bits test. This has the added benefit of working with any constant that is materializable as a 32bits immediate, not just the ones that can leverage the high register trick, as demonstrated by the test case in test-shrink.ll using the constant 2049 . Reviewers: craig.topper, niravd, spatel, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42646 llvm-svn: 323690
200 lines
4.7 KiB
C++
200 lines
4.7 KiB
C++
//===- X86MacroFusion.cpp - X86 Macro Fusion ------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file contains the X86 implementation of the DAG scheduling
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/// mutation to pair instructions back to back.
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//
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//===----------------------------------------------------------------------===//
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#include "X86MacroFusion.h"
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#include "X86Subtarget.h"
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#include "llvm/CodeGen/MacroFusion.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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using namespace llvm;
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/// \brief Check if the instr pair, FirstMI and SecondMI, should be fused
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/// together. Given SecondMI, when FirstMI is unspecified, then check if
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/// SecondMI may be part of a fused pair at all.
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static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
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const TargetSubtargetInfo &TSI,
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const MachineInstr *FirstMI,
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const MachineInstr &SecondMI) {
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const X86Subtarget &ST = static_cast<const X86Subtarget&>(TSI);
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// Check if this processor supports macro-fusion.
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if (!ST.hasMacroFusion())
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return false;
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enum {
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FuseTest,
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FuseCmp,
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FuseInc
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} FuseKind;
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unsigned FirstOpcode = FirstMI
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? FirstMI->getOpcode()
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: static_cast<unsigned>(X86::INSTRUCTION_LIST_END);
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unsigned SecondOpcode = SecondMI.getOpcode();
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switch (SecondOpcode) {
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default:
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return false;
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case X86::JE_1:
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case X86::JNE_1:
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case X86::JL_1:
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case X86::JLE_1:
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case X86::JG_1:
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case X86::JGE_1:
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FuseKind = FuseInc;
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break;
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case X86::JB_1:
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case X86::JBE_1:
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case X86::JA_1:
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case X86::JAE_1:
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FuseKind = FuseCmp;
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break;
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case X86::JS_1:
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case X86::JNS_1:
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case X86::JP_1:
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case X86::JNP_1:
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case X86::JO_1:
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case X86::JNO_1:
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FuseKind = FuseTest;
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break;
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}
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switch (FirstOpcode) {
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default:
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return false;
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case X86::TEST8rr:
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case X86::TEST16rr:
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case X86::TEST32rr:
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case X86::TEST64rr:
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case X86::TEST8ri:
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case X86::TEST16ri:
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case X86::TEST32ri:
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case X86::TEST32i32:
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case X86::TEST64i32:
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case X86::TEST64ri32:
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case X86::TEST8mr:
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case X86::TEST16mr:
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case X86::TEST32mr:
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case X86::TEST64mr:
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case X86::AND16i16:
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case X86::AND16ri:
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case X86::AND16ri8:
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case X86::AND16rm:
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case X86::AND16rr:
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case X86::AND32i32:
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case X86::AND32ri:
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case X86::AND32ri8:
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case X86::AND32rm:
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case X86::AND32rr:
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case X86::AND64i32:
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case X86::AND64ri32:
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case X86::AND64ri8:
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case X86::AND64rm:
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case X86::AND64rr:
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case X86::AND8i8:
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case X86::AND8ri:
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case X86::AND8rm:
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case X86::AND8rr:
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return true;
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case X86::CMP16i16:
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case X86::CMP16ri:
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case X86::CMP16ri8:
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case X86::CMP16rm:
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case X86::CMP16rr:
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case X86::CMP32i32:
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case X86::CMP32ri:
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case X86::CMP32ri8:
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case X86::CMP32rm:
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case X86::CMP32rr:
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case X86::CMP64i32:
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case X86::CMP64ri32:
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case X86::CMP64ri8:
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case X86::CMP64rm:
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case X86::CMP64rr:
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case X86::CMP8i8:
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case X86::CMP8ri:
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case X86::CMP8rm:
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case X86::CMP8rr:
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case X86::ADD16i16:
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case X86::ADD16ri:
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case X86::ADD16ri8:
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case X86::ADD16ri8_DB:
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case X86::ADD16ri_DB:
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case X86::ADD16rm:
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case X86::ADD16rr:
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case X86::ADD16rr_DB:
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case X86::ADD32i32:
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case X86::ADD32ri:
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case X86::ADD32ri8:
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case X86::ADD32ri8_DB:
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case X86::ADD32ri_DB:
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case X86::ADD32rm:
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case X86::ADD32rr:
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case X86::ADD32rr_DB:
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case X86::ADD64i32:
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case X86::ADD64ri32:
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case X86::ADD64ri32_DB:
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case X86::ADD64ri8:
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case X86::ADD64ri8_DB:
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case X86::ADD64rm:
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case X86::ADD64rr:
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case X86::ADD64rr_DB:
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case X86::ADD8i8:
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case X86::ADD8mi:
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case X86::ADD8mr:
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case X86::ADD8ri:
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case X86::ADD8rm:
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case X86::ADD8rr:
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case X86::SUB16i16:
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case X86::SUB16ri:
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case X86::SUB16ri8:
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case X86::SUB16rm:
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case X86::SUB16rr:
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case X86::SUB32i32:
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case X86::SUB32ri:
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case X86::SUB32ri8:
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case X86::SUB32rm:
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case X86::SUB32rr:
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case X86::SUB64i32:
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case X86::SUB64ri32:
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case X86::SUB64ri8:
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case X86::SUB64rm:
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case X86::SUB64rr:
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case X86::SUB8i8:
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case X86::SUB8ri:
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case X86::SUB8rm:
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case X86::SUB8rr:
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return FuseKind == FuseCmp || FuseKind == FuseInc;
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case X86::INC16r:
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case X86::INC32r:
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case X86::INC64r:
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case X86::INC8r:
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case X86::DEC16r:
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case X86::DEC32r:
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case X86::DEC64r:
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case X86::DEC8r:
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return FuseKind == FuseInc;
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case X86::INSTRUCTION_LIST_END:
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return true;
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}
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}
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namespace llvm {
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std::unique_ptr<ScheduleDAGMutation>
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createX86MacroFusionDAGMutation () {
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return createBranchMacroFusionDAGMutation(shouldScheduleAdjacent);
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}
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} // end namespace llvm
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