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Daniel Sanders 08464524c3 [ARM][GISel] PR35965 Constrain RegClasses of nested instructions built from Dst Pattern 
Summary:
Apparently, we missed on constraining register classes of VReg-operands of all the instructions
built from a destination pattern but the root (top-level) one. The issue exposed itself
while selecting G_FPTOSI for armv7: the corresponding pattern generates VTOSIZS wrapped
into COPY_TO_REGCLASS, so top-level COPY_TO_REGCLASS gets properly constrained,
while nested VTOSIZS (or rather its destination virtual register to be exact) does not.

Fixing this by issuing GIR_ConstrainSelectedInstOperands for every nested GIR_BuildMI.

https://bugs.llvm.org/show_bug.cgi?id=35965
rdar://problem/36886530

Patch by Roman Tereshin

Reviewers: dsanders, qcolombet, rovka, bogner, aditya_nandakumar, volkan

Reviewed By: dsanders, qcolombet, rovka

Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D42565

llvm-svn: 323692
2018-01-29 21:09:12 +00:00
..
GlobalISel
[ARM][GISel] PR35965 Constrain RegClasses of nested instructions built from Dst Pattern
2018-01-29 21:09:12 +00:00
Windows
[ARM] Call __chkstk for dynamic stack allocation in all windows environments
2018-01-24 06:40:11 +00:00
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test: modernise ARM CodeGen tests
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test: modernise ARM CodeGen tests
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[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
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llvm-dwarfdump: Make -brief the default and add a -verbose option instead.
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aeabi-read-tp.ll
ARM: support -mlong-calls with AEABI TLS on ELF
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aggregate-padding.ll
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alias_store.ll
Fix PR31896.
2017-02-21 20:17:34 +00:00
aliases.ll
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align-sp-adjustment.ll
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align.ll
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alloc-no-stack-realign.ll
[DAGCombine] Disable finding better chains for stores at O0
2017-11-28 04:07:59 +00:00
alloca-align.ll
RegScavenging: Add scavengeRegisterBackwards()
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alloca.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
and-cmpz.ll
[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently
2016-12-15 09:38:59 +00:00
and-load-combine.ll
[DAGCombine] Fix for PR37563
2018-01-05 08:47:23 +00:00
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NFC: I simply added CHECK-LABEL to prevent false matches in the tests.
2017-07-07 13:41:33 +00:00
arguments-nosplit-i64.ll
NFC: I simply added CHECK-LABEL to prevent false matches in the tests.
2017-07-07 13:41:33 +00:00
arguments.ll
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arm32-round-conv.ll
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arm-abi-attr.ll
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2017-06-30 00:03:54 +00:00
arm-and-tst-peephole.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
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arm-eabi.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
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arm-insert-subvector.ll
[ARM] Check for assembler instructions in test.
2017-08-23 11:53:24 +00:00
arm-macho-tail.ll
ARM: use an external relocation for calls from MachO ARM mode.
2017-08-18 19:13:56 +00:00
arm-modifier.ll
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arm-position-independence-jump-table.ll
[ARM] Place jump table as the first operand in additions
2017-11-13 11:56:48 +00:00
arm-position-independence.ll
[ARM] Make RWPI use movw/movt when available
2017-02-07 13:07:12 +00:00
arm-returnaddr.ll
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arm-shrink-wrapping-linux.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
arm-shrink-wrapping.ll
Fix test broken by r304020
2017-05-26 22:11:18 +00:00
arm-storebytesmerge.ll
[ARM][AArch64][DAG] Reenable post-legalize store merge
2017-12-06 15:30:13 +00:00
arm-ttype-target2.ll
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ARMLoadStoreDBG.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
armv4.ll
Fix ARMv4 support
2017-08-28 20:20:47 +00:00
atomic-64bit.ll
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atomic-cmp.ll
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atomic-cmpxchg.ll
[LegalizeDAG] Fix ATOMIC_CMP_SWAP_WITH_SUCCESS legalization.
2018-01-17 22:04:36 +00:00
atomic-load-store.ll
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atomic-op.ll
Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding""
2017-10-03 16:59:13 +00:00
atomic-ops-v8.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
atomicrmw_minmax.ll
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available_externally.ll
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avoid-cpsr-rmw.ll
[SimplifyCFG] Avoid quadratic on a predecessors number behavior in instruction sinking.
2017-12-21 01:22:13 +00:00
bfc.ll
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bfi.ll
[ARM] Prefer BIC over BFC in ARM mode.
2017-04-07 22:01:23 +00:00
bfx.ll
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bic.ll
[ARM] Prefer BIC over BFC in ARM mode.
2017-04-07 22:01:23 +00:00
bicZext.ll
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big-endian-eh-unwind.ll
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big-endian-neon-bitconv.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
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big-endian-vector-callee.ll
[ARM] Split 128-bit vectors in BUILD_VECTOR lowering
2016-12-14 20:44:38 +00:00
big-endian-vector-caller.ll
…
bit-reverse-to-rbit.ll
…
bits.ll
…
bool-ext-inc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
bswap16.ll
…
bswap-inline-asm.ll
…
build-attributes-encoding.s
…
build-attributes-fn-attr0.ll
…
build-attributes-fn-attr1.ll
…
build-attributes-fn-attr2.ll
…
build-attributes-fn-attr3.ll
…
build-attributes-fn-attr4.ll
…
build-attributes-fn-attr5.ll
…
build-attributes-fn-attr6.ll
This is a 1 character fix for an ARM build attribute test (r284571): the
2016-11-01 15:59:37 +00:00
build-attributes-optimization-minsize.ll
…
build-attributes-optimization-mixed.ll
…
build-attributes-optimization-optnone.ll
…
build-attributes-optimization-optsize.ll
…
build-attributes-optimization.ll
…
build-attributes.ll
[ARM] Add support for armv7e-m to the .arch directive
2017-11-29 10:12:15 +00:00
bx_fold.ll
…
byval_load_align.ll
…
byval-align.ll
…
cache-intrinsic.ll
…
call_nolink.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
call-noret-minsize.ll
…
call-noret.ll
…
call-tc.ll
[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently
2016-12-15 09:38:59 +00:00
call.ll
…
carry.ll
…
cdp2.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
cdp.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
cfi-alignment.ll
…
clang-section.ll
Add support for #pragma clang section
2017-06-05 10:09:13 +00:00
clz.ll
…
cmn.ll
…
cmp1-peephole-thumb.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
cmp2-peephole-thumb.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
cmp.ll
[ARM] Swap cmp operands for automatic shifts
2017-10-25 08:33:06 +00:00
cmpxchg-idioms.ll
…
cmpxchg-O0-be.ll
ARM: fix big-endian 64-bit cmpxchg.
2017-06-30 19:51:02 +00:00
cmpxchg-O0.ll
[LegalizeDAG] Fix ATOMIC_CMP_SWAP_WITH_SUCCESS legalization.
2018-01-17 22:04:36 +00:00
cmpxchg-weak.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
coalesce-dbgvalue.ll
Canonicalize the representation of empty an expression in DIGlobalVariableExpression
2017-08-30 18:06:51 +00:00
coalesce-subregs.ll
…
code-placement.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
coff-no-dead-strip.ll
test: fix ARM tests harder
2018-01-20 01:26:46 +00:00
combine-movc-sub.ll
…
combine-vmovdrr.ll
…
commute-movcc.ll
…
compare-call.ll
…
constant-island-crash.ll
…
constant-islands-cfg.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
constant-islands.ll
…
constantfp.ll
Rewrite ARM execute only support to avoid the use of a command line flag and unqualified ARMSubtarget lookup.
2017-07-01 02:55:22 +00:00
constantpool-align.ll
…
constantpool-promote-dbg.ll
[ARM] Temporarily disable globals promotion to constant pools to prevent miscompilation
2017-05-23 19:38:37 +00:00
constantpool-promote-duplicate.ll
ARM: track globals promoted to coalesced const pool entries
2017-09-07 04:00:13 +00:00
constantpool-promote-ldrh.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
constantpool-promote.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
constants.ll
…
copy-cpsr.ll
…
copy-paired-reg.ll
…
cortex-a57-misched-alu.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
cortex-a57-misched-basic.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
cortex-a57-misched-ldm-wrback.ll
[CodeGen] Add dependency printer
2017-07-12 15:30:59 +00:00
cortex-a57-misched-ldm.ll
[CodeGen] Add dependency printer
2017-07-12 15:30:59 +00:00
cortex-a57-misched-stm-wrback.ll
[CodeGen] Add dependency printer
2017-07-12 15:30:59 +00:00
cortex-a57-misched-stm.ll
[ARM] Cortex-A57 scheduling model for ARM backend (AArch32)
2017-06-02 08:53:19 +00:00
cortex-a57-misched-vadd.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
cortex-a57-misched-vfma.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
cortex-a57-misched-vldm-wrback.ll
[CodeGen] Add dependency printer
2017-07-12 15:30:59 +00:00
cortex-a57-misched-vldm.ll
[CodeGen] Add dependency printer
2017-07-12 15:30:59 +00:00
cortex-a57-misched-vstm-wrback.ll
[CodeGen] Add dependency printer
2017-07-12 15:30:59 +00:00
cortex-a57-misched-vstm.ll
[ARM] Cortex-A57 scheduling model for ARM backend (AArch32)
2017-06-02 08:53:19 +00:00
cortex-a57-misched-vsub.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
cortexr52-misched-basic.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
crash-greedy-v6.ll
…
crash-greedy.ll
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
crash-O0.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
crash-on-pow2-shufflevector.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
crash-shufflevector.ll
…
crash.ll
…
crc32.ll
…
cse-call.ll
[ARM] Call setBooleanContents(ZeroOrOneBooleanContent)
2017-08-22 11:02:37 +00:00
cse-flags.ll
…
cse-ldrlit.ll
…
cse-libcalls.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
ctor_order.ll
Unified logic for computing target ABI in backend and front end by moving this common code to Support/TargetParser.
2017-06-30 00:03:54 +00:00
ctors_dtors.ll
Unified logic for computing target ABI in backend and front end by moving this common code to Support/TargetParser.
2017-06-30 00:03:54 +00:00
cttz_vector.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
cttz.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
cxx-tlscc.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
dag-combine-ldst.ll
Elide stores which are overwritten without being observed.
2017-05-16 19:43:56 +00:00
dagcombine-anyexttozeroext.ll
…
dagcombine-concatvector.ll
…
darwin-eabi.ll
…
darwin-tls-preserved.ll
ARM: TLS calling convention doesn't preserve r9 or r12 on Darwin.
2017-04-19 18:07:54 +00:00
darwin-tls.ll
…
data-in-code-annotations.ll
…
dbg-range-extension.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
dbg.ll
…
DbgValueOtherTargets.test
…
debug-frame-large-stack.ll
…
debug-frame-no-debug.ll
…
debug-frame-vararg.ll
…
debug-frame.ll
…
debug-info-arg.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
debug-info-blocks.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
debug-info-branch-folding.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
debug-info-d16-reg.ll
Remove the obsolete offset parameter from @llvm.dbg.value
2017-07-28 20:21:02 +00:00
debug-info-no-frame.ll
…
debug-info-qreg.ll
[DebugInfo] Align comments in debug_loc section
2018-01-05 22:20:30 +00:00
debug-info-s16-reg.ll
Remove the obsolete offset parameter from @llvm.dbg.value
2017-07-28 20:21:02 +00:00
debug-info-sreg2.ll
[DebugInfo] Unify dumping of address ranges
2018-01-16 11:17:57 +00:00
debug-segmented-stacks.ll
Fix ARMv4 support
2017-08-28 20:20:47 +00:00
debugtrap.ll
…
default-float-abi.ll
…
default-reloc.ll
…
deprecated-asm.s
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
deps-fix.ll
Separate ExecutionDepsFix into 4 parts:
2018-01-22 10:05:23 +00:00
disable-fp-elim.ll
…
disable-tail-calls.ll
…
div.ll
[ARM] Add support for armv7ve triple in llvm (PR31358).
2017-02-09 23:29:14 +00:00
divmod-eabi.ll
ARM: use divmod libcalls on embedded MachO platforms too.
2017-05-08 20:00:14 +00:00
divmod-hwdiv.ll
[ARM] Check for correct HW div when lowering divmod
2017-04-18 08:32:27 +00:00
divmod.ll
ARM: use divmod libcalls on embedded MachO platforms too.
2017-05-08 20:00:14 +00:00
domain-conv-vmovs.ll
…
dsp-mlal.ll
[ARM] Add codegen for SMMULR, SMMLAR and SMMLSR
2018-01-12 09:24:41 +00:00
dwarf-eh.ll
Remove Bitrig: LLVM Changes
2017-07-21 22:48:47 +00:00
dwarf-unwind.ll
…
dyn-stackalloc.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
early-cfi-sections.ll
Emit .cfi_sections before the first .cfi_startproc
2017-01-02 18:05:27 +00:00
eh-dispcont.ll
…
eh-resume-darwin.ll
…
ehabi-filters.ll
…
ehabi-handlerdata-nounwind.ll
…
ehabi-handlerdata.ll
…
ehabi-no-landingpad.ll
…
ehabi-unwind.ll
…
ehabi.ll
[ARM] Use dwarf exception handling on MinGW
2017-11-17 08:04:40 +00:00
elf-lcomm-align.ll
…
emit-big-cst.ll
…
emutls1.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
emutls_generic.ll
[ARM] Allow using emulated tls on platforms other than ELF
2017-12-04 09:08:55 +00:00
emutls.ll
…
execute-only-big-stack-frame.ll
Rewrite ARM execute only support to avoid the use of a command line flag and unqualified ARMSubtarget lookup.
2017-07-01 02:55:22 +00:00
execute-only-section.ll
Rewrite ARM execute only support to avoid the use of a command line flag and unqualified ARMSubtarget lookup.
2017-07-01 02:55:22 +00:00
execute-only.ll
[ARM] Place jump table as the first operand in additions
2017-11-13 11:56:48 +00:00
expand-pseudos.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
extload-knownzero.ll
…
extloadi1.ll
…
fabs-neon.ll
…
fabs-to-bfc.ll
…
fabss.ll
…
fadds.ll
…
fast-isel-align.ll
[ARM] Use VCMP, not VCMPE, for floating point equality comparisons
2017-02-13 12:32:47 +00:00
fast-isel-binary.ll
…
fast-isel-br-const.ll
…
fast-isel-br-phi.ll
…
fast-isel-call-multi-reg-return.ll
…
fast-isel-call.ll
…
fast-isel-cmp-imm.ll
[ARM] Use VCMP, not VCMPE, for floating point equality comparisons
2017-02-13 12:32:47 +00:00
fast-isel-conversion.ll
…
fast-isel-crash2.ll
…
fast-isel-crash.ll
…
fast-isel-deadcode.ll
…
fast-isel-ext.ll
…
fast-isel-fold.ll
…
fast-isel-frameaddr.ll
…
fast-isel-GEP-coalesce.ll
…
fast-isel-icmp.ll
…
fast-isel-indirectbr.ll
…
fast-isel-inline-asm.ll
…
fast-isel-intrinsic.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
fast-isel-ldr-str-arm.ll
…
fast-isel-ldr-str-thumb-neg-index.ll
…
fast-isel-ldrh-strh-arm.ll
…
fast-isel-load-store-verify.ll
…
fast-isel-mvn.ll
…
fast-isel-pic.ll
…
fast-isel-pie.ll
…
fast-isel-pred.ll
…
fast-isel-redefinition.ll
…
fast-isel-remat-same-constant.ll
…
fast-isel-ret.ll
…
fast-isel-select.ll
…
fast-isel-shift-materialize.ll
…
fast-isel-shifter.ll
…
fast-isel-static.ll
…
fast-isel-update-valuemap-for-extract.ll
…
fast-isel-vaddd.ll
…
fast-isel-vararg.ll
…
fast-isel.ll
…
fast-tail-call.ll
…
fastcc-vfp.ll
…
fastisel-gep-promote-before-add.ll
…
fastisel-thumb-litpool.ll
AsmPrinter: mark the beginning and the end of a function in verbose mode
2017-05-23 21:22:16 +00:00
fcopysign.ll
…
fdivs.ll
…
fence-singlethread.ll
Enhance synchscope representation
2017-07-11 22:23:00 +00:00
fixunsdfdi.ll
…
flag-crash.ll
…
float-helpers.s
[ARM] Add test to check pcs of ARM ABI runtime floating point helpers
2017-07-28 09:21:00 +00:00
floorf.ll
…
fmacs.ll
…
fmdrr-fmrrd.ll
…
fmscs.ll
…
fmuls.ll
…
fnattr-trap.ll
…
fnegs.ll
…
fnmacs.ll
…
fnmscs.ll
[ARM] Add missing selection patterns for vnmla
2017-09-22 09:50:52 +00:00
fnmul.ll
…
fnmuls.ll
…
fold-const.ll
…
fold-stack-adjust.ll
Codegen: Make chains from trellis-shaped CFGs
2017-02-15 19:49:14 +00:00
formal.ll
…
fp16-args.ll
…
fp16-instructions.ll
[ARM] Armv8.2-A FP16 code generation (part 1/3)
2018-01-26 09:26:40 +00:00
fp16-promote.ll
[ARM][AArch64][DAG] Reenable post-legalize store merge
2017-12-06 15:30:13 +00:00
fp16-v3.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
fp16.ll
…
fp_convert.ll
…
fp-arg-shuffle.ll
…
fp-fast.ll
…
fp-only-sp.ll
ARM: make sure FastISel bails on f64 operations for Cortex-M4.
2017-02-23 22:35:00 +00:00
fp.ll
…
fparith.ll
…
fpcmp_ueq.ll
[ARM] Use VCMP, not VCMPE, for floating point equality comparisons
2017-02-13 12:32:47 +00:00
fpcmp-f64-neon-opt.ll
…
fpcmp-opt.ll
[ARM] Prefer BIC over BFC in ARM mode.
2017-04-07 22:01:23 +00:00
fpcmp.ll
[ARM] Use VCMP, not VCMPE, for floating point equality comparisons
2017-02-13 12:32:47 +00:00
fpconsts.ll
…
fpconv.ll
…
fpmem.ll
…
fpoffset_overflow.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
fpow.ll
…
fpowi.ll
test: modernise ARM CodeGen tests
2016-12-27 18:35:19 +00:00
fpscr-intrinsics.ll
[ARM] Reapply r296865 "[ARM] fpscr read/write intrinsics not aware of each other""
2017-03-07 11:17:53 +00:00
fptoint.ll
…
frame-register.ll
…
fsubs.ll
…
func-argpassing-endian.ll
…
fusedMAC.ll
…
gep-optimization.ll
…
ghc-tcreturn-lowered.ll
…
global-merge-1.ll
Revert "Use private linkage for MergedGlobals variables" on Darwin.
2016-11-11 17:50:09 +00:00
global-merge-addrspace.ll
…
global-merge-dllexport.ll
[GlobalMerge] Don't merge dllexport globals
2018-01-24 06:40:04 +00:00
global-merge-external.ll
[GlobalMerge] Don't merge dllexport globals
2018-01-24 06:40:04 +00:00
global-merge.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
globals.ll
…
gpr-paired-spill-thumbinst.ll
…
gpr-paired-spill.ll
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
2017-03-14 00:34:14 +00:00
gv-stubs-crash.ll
…
half.ll
…
hardfloat_neon.ll
…
hello.ll
…
hfa-in-contiguous-registers.ll
…
hidden-vis-2.ll
…
hidden-vis-3.ll
…
hidden-vis.ll
…
hints.ll
…
i1.ll
[ARM] Call setBooleanContents(ZeroOrOneBooleanContent)
2017-08-22 11:02:37 +00:00
iabs.ll
…
ifconv-kills.ll
…
ifconv-regmask.ll
…
ifcvt1.ll
…
ifcvt2.ll
…
ifcvt3.ll
…
ifcvt4.ll
…
ifcvt5.ll
…
ifcvt6.ll
…
ifcvt7.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
ifcvt8.ll
…
ifcvt9.ll
…
ifcvt10.ll
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
2017-03-14 00:34:14 +00:00
ifcvt11.ll
…
ifcvt12.ll
…
ifcvt_canFallThroughTo.mir
Move tests to the correct place
2018-01-19 06:08:15 +00:00
ifcvt_diamond_unanalyzable.mir
Move tests to the correct place
2018-01-19 06:08:15 +00:00
ifcvt_forked_diamond_unanalyzable.mir
Move tests to the correct place
2018-01-19 06:08:15 +00:00
ifcvt_simple_bad_zero_prob_succ.mir
Move tests to the correct place
2018-01-19 06:08:15 +00:00
ifcvt_simple_unanalyzable.mir
Move tests to the correct place
2018-01-19 06:08:15 +00:00
ifcvt_triangleWoCvtToNextEdge.mir
Move tests to the correct place
2018-01-19 06:08:15 +00:00
ifcvt-branch-weight-bug.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
ifcvt-branch-weight.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
ifcvt-callback.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
ifcvt-dead-def.ll
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
ifcvt-iter-indbr.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
ifcvt-regmask-noreturn.ll
…
illegal-bitfield-loadstore.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
illegal-vector-bitcast.ll
…
imm-peephole-arm.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
imm-peephole-thumb.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
imm.ll
…
immcost.ll
…
indirect-hidden.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
indirect-reg-input.ll
…
indirectbr-2.ll
…
indirectbr-3.ll
[IfConversion] Maintain the CFG when predicating/merging blocks in IfConvert*
2017-08-11 06:57:08 +00:00
indirectbr.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
inline-diagnostics.ll
…
inlineasm2.ll
…
inlineasm3.ll
…
inlineasm4.ll
…
inlineasm-64bit.ll
…
inlineasm-global.ll
…
inlineasm-imm-arm.ll
…
inlineasm-imm-thumb2.ll
…
inlineasm-imm-thumb.ll
…
inlineasm-ldr-pseudo.ll
…
inlineasm-switch-mode-oneway-from-arm.ll
…
inlineasm-switch-mode-oneway-from-thumb.ll
…
inlineasm-switch-mode.ll
…
inlineasm-X-allocation.ll
…
inlineasm-X-constraint.ll
…
inlineasm.ll
[ARM] 't' asm constraint should accept i32
2017-11-16 23:38:17 +00:00
insn-sched1.ll
…
int-to-fp.ll
…
integer_insertelement.ll
…
interrupt-attr.ll
…
interval-update-remat.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
interwork.ll
…
intrinsics-coprocessor.ll
[ARM] Avoid using ARM instructions in Thumb mode
2017-01-31 14:35:01 +00:00
intrinsics-crypto.ll
…
intrinsics-memory-barrier.ll
…
intrinsics-overflow.ll
[ARM] Optimize {s,u}{add,sub}.with.overflow.
2018-01-17 19:19:05 +00:00
intrinsics-v8.ll
…
invalid-target.ll
…
invalidated-save-point.ll
[Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default.
2017-06-06 08:16:19 +00:00
invoke-donothing-assert.ll
…
isel-v8i32-crash.ll
…
ispositive.ll
…
jump-table-islands-split.ll
…
jump-table-islands.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
jump-table-tbh.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
jumptable-label.ll
…
krait-cpu-div-attribute.ll
…
large-stack.ll
…
ldaex-stlex.ll
…
ldc2l.ll
…
ldm-base-writeback.ll
…
ldm-stm-base-materialization.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
ldm-stm-i256.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
ldm.ll
…
ldr_ext.ll
…
ldr_frame.ll
…
ldr_post.ll
…
ldr_pre.ll
…
ldr.ll
…
ldrd-memoper.ll
…
ldrd.ll
Add address space mangling to lifetime intrinsics
2017-04-10 20:18:21 +00:00
ldst-f32-2-i32.ll
…
ldstrex-m.ll
…
ldstrex.ll
…
legalize-unaligned-load.ll
Delete Default and JITDefault code models
2017-08-03 02:16:21 +00:00
lit.local.cfg
…
litpool-licm.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
load_i1_select.ll
…
load_store_multiple.ll
[ARM] Fix isRenamable flag setting on expanded VSTMDIA opcode.
2017-12-14 18:06:25 +00:00
load_store_opt_kill.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
load-address-masked.ll
…
load-arm.ll
ARM: add extra test for addrmode folding.
2017-05-03 16:54:30 +00:00
load-combine-big-endian.ll
[DAGCombiner] Support {a|s}ext, {a|z|s}ext load nodes in load combine
2017-03-01 18:12:29 +00:00
load-combine.ll
[DAGCombiner] Support {a|s}ext, {a|z|s}ext load nodes in load combine
2017-03-01 18:12:29 +00:00
load-global2.ll
[arm] Fix Unnecessary reloads from GOT.
2017-11-13 20:45:38 +00:00
load-global.ll
…
load-store-flags.ll
…
load.ll
…
local-call.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
log2_not_readnone.ll
…
long_shift.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
long-setcc.ll
[ARM] Add tests for D34515
2017-12-15 09:24:46 +00:00
long.ll
…
longMAC.ll
[ARM] Fix mixup between Lo and Hi in SMLALBB formation.
2017-03-25 00:13:24 +00:00
loopvectorize_pr33804.ll
[LoopVectorizer] Add more testcases for PR33804.
2017-09-18 17:28:15 +00:00
lowerMUL-newload.ll
[SelectionDAG] [ARM CodeGen] Fix chain information of LowerMUL
2017-04-06 20:22:51 +00:00
lsr-code-insertion.ll
…
lsr-icmp-imm.ll
…
lsr-scale-addr-mode.ll
…
lsr-unfolded-offset.ll
…
machine-copyprop.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
machine-cse-cmp.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
machine-licm.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
macho-extern-hidden.ll
…
macho-frame-offset.ll
…
MachO-subtypes.ll
…
mature-mc-support.ll
[LLC] Add an inline assembly diagnostics handler.
2017-02-03 11:14:39 +00:00
mem.ll
…
memcpy-inline.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
memcpy-ldm-stm.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
memcpy-no-inline.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
memfunc.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
memset-inline.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
MergeConsecutiveStores.ll
…
metadata-default.ll
…
metadata-short-enums.ll
…
metadata-short-wchar.ll
…
minmax.ll
…
minsize-call-cse.ll
…
minsize-imms.ll
…
minsize-litpools.ll
…
misched-copy-arm.ll
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
misched-fp-basic.ll
CodeGen: Rename DEBUG_TYPE to match passnames
2017-05-25 21:26:32 +00:00
misched-fusion-aes.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
misched-int-basic-thumb2.mir
[CodeGen] Print RegClasses on MI in verbose mode
2018-01-18 17:59:06 +00:00
misched-int-basic.mir
[CodeGen] Print RegClasses on MI in verbose mode
2018-01-18 17:59:06 +00:00
mls.ll
…
movcc-double.ll
…
movt-movw-global.ll
…
movt.ll
[ARM] Enable Cortex-M23 and Cortex-M33 support.
2017-02-01 11:55:03 +00:00
msr-it-block.ll
[ARM] Fix incorrect mask bits in MSR encoding for write_register intrinsic
2017-02-10 17:41:08 +00:00
mul_const.ll
…
mul.ll
…
mulhi.ll
…
mult-alt-generic-arm.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
mvn.ll
…
named-reg-alloc.ll
…
named-reg-notareg.ll
…
negate-i1.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
negative-offset.ll
…
neon_arith1.ll
…
neon_cmp.ll
…
neon_div.ll
ARM: fix vectorized division on WoA
2017-01-27 03:41:53 +00:00
neon_fpconv.ll
…
neon_ld1.ll
…
neon_ld2.ll
…
neon_minmax.ll
…
neon_shift.ll
…
neon_spill.ll
…
neon_vabs.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
neon_vshl_minint.ll
…
neon-fma.ll
…
neon-spfp.ll
…
neon-v8.1a.ll
…
nest-register.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
no_redundant_trunc_for_cmp.ll
…
no-arm-mode.ll
[ARM] Emit error when ARM exec mode is not available.
2017-08-09 15:39:10 +00:00
no-cfi.ll
Canonicalize the representation of empty an expression in DIGlobalVariableExpression
2017-08-30 18:06:51 +00:00
no-cmov2bfi.ll
[ARM] Fix computeKnownBits for ARMISD::CMOV
2017-03-23 16:47:47 +00:00
no-fpscr-liveness.ll
LiveIntervalAnalysis: Fix alias regunit reserved definition
2017-09-01 18:36:26 +00:00
no-fpu.ll
…
no-tail-call.ll
…
none-macho-v4t.ll
…
none-macho.ll
…
noopt-dmb-v7.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
nop_concat_vectors.ll
…
noreturn.ll
…
null-streamer.ll
…
opt-shuff-tstore.ll
…
optimize-dmbs-v7.ll
…
optselect-regclass.ll
…
out-of-registers.ll
…
overflow-intrinsic-optimizations.ll
[ARM] Fix perf regression in compare optimization.
2018-01-19 17:46:27 +00:00
pack.ll
…
peephole-bitcast.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
peephole-phi.mir
PeepholeOptimizer: Fix for vregs without defs
2018-01-11 22:30:43 +00:00
pei-swiftself.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
phi.ll
Turn on -addr-sink-using-gep by default.
2017-04-06 22:42:18 +00:00
pic.ll
…
pie.ll
…
plt-relative-reloc.ll
…
popcnt.ll
…
pr3502.ll
…
pr13249.ll
…
pr18364-movw.ll
…
pr25317.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
pr25838.ll
…
pr26669.ll
…
pr32545.ll
[SDAG] Fix visitAND optimization to deal with vector extract case again.
2017-04-06 19:05:41 +00:00
pr32578.ll
ARM: Fix PR32578
2017-11-28 01:17:52 +00:00
pr34045-2.ll
[ARM] Use ADDCARRY / SUBCARRY
2017-12-11 12:13:45 +00:00
pr34045.ll
[ARM] Use ADDCARRY / SUBCARRY
2017-12-11 12:13:45 +00:00
pr35103.ll
[ARM] Use ADDCARRY / SUBCARRY
2017-12-11 12:13:45 +00:00
PR15053.ll
…
PR32721_ifcvt_triangle_unanalyzable.mir
Move tests to the correct place
2018-01-19 06:08:15 +00:00
PR35379.ll
[ARM] Fix PR35379 - incorrect unwind information when compiling with -Oz
2018-01-08 14:47:19 +00:00
preferred-align.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
prefetch.ll
…
prera-ldst-aliasing.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
prera-ldst-insertpt.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
print-memb-operand.ll
…
private.ll
…
rbit.ll
[SelectionDAG] Add support for BITREVERSE constant folding
2017-01-16 13:39:00 +00:00
readcyclecounter.ll
…
readtp.ll
Add newline to end of test file. NFC.
2017-09-14 14:48:59 +00:00
reg_sequence.ll
…
regpair_hint_phys.ll
…
rem_crash.ll
…
ret0.ll
…
ret_arg1.ll
…
ret_arg2.ll
…
ret_arg3.ll
…
ret_arg4.ll
…
ret_arg5.ll
…
ret_f32_arg2.ll
…
ret_f32_arg5.ll
…
ret_f64_arg2.ll
…
ret_f64_arg_reg_split.ll
…
ret_f64_arg_split.ll
…
ret_f64_arg_stack.ll
…
ret_i64_arg2.ll
…
ret_i64_arg3.ll
…
ret_i64_arg_split.ll
…
ret_i128_arg2.ll
…
ret_sret_vector.ll
…
ret_void.ll
…
returned-ext.ll
…
returned-trunc-tail-calls.ll
…
rev.ll
The automatic CHECK: to CHECK-LABEL: conversion, back in 2013,
2017-02-25 15:17:16 +00:00
ror.ll
[DAGCombiner] visitRotate patch to optimize pair of ROTR/ROTL instructions into one with combined shift operand.
2017-07-05 17:55:42 +00:00
rotate.ll
…
saxpy10-a9.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
sbfx.ll
…
scavenging.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
sched-it-debug-nodes.mir
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
section-name.ll
…
section.ll
…
segmented-stacks-dynamic.ll
Fix ARMv4 support
2017-08-28 20:20:47 +00:00
segmented-stacks.ll
Fix ARMv4 support
2017-08-28 20:20:47 +00:00
select_const.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
select_xform.ll
[DAGCombiner] fold binops with constant into select-of-constants
2017-03-01 22:51:31 +00:00
select-imm.ll
[ARM] Add tests for D34515
2017-12-15 09:24:46 +00:00
select-undef.ll
…
select.ll
…
setcc-logic.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
setcc-type-mismatch.ll
…
setjmp_longjmp.ll
[ARM] Restore the right frame pointer register in Int_eh_sjlj_longjmp
2017-09-28 19:04:30 +00:00
shift-combine.ll
[DAGCombine] Revert r321259
2017-12-22 08:36:25 +00:00
shift-i64.ll
[ARM] Expand long shifts for Thumb1 to __aeabi_ calls
2018-01-24 18:00:57 +00:00
shifter_operand.ll
…
shuffle.ll
…
sincos.ll
[SelectionDAG] Allow sin/cos -> sincos optimization on GNU triples w/ just -fno-math-errno
2017-06-12 17:15:41 +00:00
single-issue-r52.mir
[CodeGen] Print RegClasses on MI in verbose mode
2018-01-18 17:59:06 +00:00
sjlj-prepare-critical-edge.ll
…
sjljeh-swifterror.ll
SjLjEHPrepare: Fix the pass for swifterror arguments
2017-03-07 20:29:02 +00:00
sjljehprepare-lower-empty-struct.ll
[ARM] Fix SJLJ exception handling when manually chosen on a platform where it isn't default
2017-09-28 19:04:14 +00:00
smml.ll
[ARM] Fix erroneous availability of SMMLS for Armv7-M
2018-01-12 09:21:09 +00:00
smul.ll
[ARM] Move SMULW[B|T] isel to DAG Combine
2017-03-14 09:13:22 +00:00
softfp-fabs-fneg.ll
[ARM] Prefer BIC over BFC in ARM mode.
2017-04-07 22:01:23 +00:00
space-directive.ll
…
special-reg-acore.ll
…
special-reg-mcore.ll
[ARM] Fix incorrect mask bits in MSR encoding for write_register intrinsic
2017-02-10 17:41:08 +00:00
special-reg-v8m-base.ll
…
special-reg-v8m-main.ll
[ARM] Unify handling of M-Class system registers
2017-07-19 12:57:16 +00:00
special-reg.ll
…
spill-q.ll
…
ssat-lower.ll
…
ssat-upper.ll
…
ssat-v4t.ll
…
ssat.ll
…
ssp-data-layout.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
stack_guard_remat.ll
Add address space mangling to lifetime intrinsics
2017-04-10 20:18:21 +00:00
stack-alignment.ll
…
stack-frame.ll
…
stack-protector-bmovpcb_call.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
stack-size-section.ll
[MC] Fix -stack-size-section on ARM
2018-01-17 09:01:29 +00:00
stackpointer.ll
…
static-addr-hoisting.ll
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
2017-03-14 00:34:14 +00:00
stc2.ll
…
stm.ll
…
str_post.ll
…
str_pre-2.ll
Unified logic for computing target ABI in backend and front end by moving this common code to Support/TargetParser.
2017-06-30 00:03:54 +00:00
str_pre.ll
…
str_trunc.ll
…
struct_byval_arm_t1_t2.ll
…
struct_byval.ll
…
struct-byval-frame-index.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
sub-cmp-peephole.ll
[ARM] Call setBooleanContents(ZeroOrOneBooleanContent)
2017-08-22 11:02:37 +00:00
sub.ll
…
subreg-remat.ll
[CodeGen] Don't print "pred:" and "opt:" in -debug output
2018-01-09 17:31:07 +00:00
subtarget-features-long-calls.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
subtarget-no-movt.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
swift-atomics.ll
…
swift-ios.ll
…
swift-return.ll
…
swift-vldm.ll
…
swifterror.ll
Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding""
2017-10-03 16:59:13 +00:00
swiftself.ll
[ARM/AArch ISel] SwiftCC: First parameters that are marked swiftself are not 'this returns'
2017-02-08 22:30:47 +00:00
switch-minsize.ll
…
sxt_rot.ll
…
t2-imm.ll
…
t2-shrink-ldrpost.ll
…
t2abs-killflags.ll
…
tail-call-builtin.ll
…
tail-call-float.ll
[ARM] Relax restriction on variadic functions for tailcall optimization
2016-11-17 10:56:58 +00:00
tail-call-weak.ll
…
tail-call.ll
[ARM] Relax restriction on variadic functions for tailcall optimization
2016-11-17 10:56:58 +00:00
tail-dup-bundle.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
tail-dup-kill-flags.ll
…
tail-dup.ll
…
tail-merge-branch-weight.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
tail-opts.ll
[BranchFolding] Tail common all identical unreachable blocks
2017-02-14 21:02:24 +00:00
tailcall-mem-intrinsics.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
taildup-branch-weight.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
test-sharedidx.ll
…
this-return.ll
…
thread_pointer.ll
test: modernise ARM CodeGen tests
2016-12-27 18:35:19 +00:00
thumb1_return_sequence.ll
[ARM] Fix an off-by-one error when restoring LR for 16-bit Thumb
2017-11-27 10:13:14 +00:00
thumb1-div.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
thumb1-ldst-opt.ll
…
thumb1-varalloc.ll
…
thumb2-it-block.ll
[NFC] Use stdin for some tests instead of positional argument.
2017-06-29 14:51:54 +00:00
thumb2-size-opt.ll
…
thumb2-size-reduction-internal-flags.ll
…
thumb_indirect_calls.ll
…
thumb-alignment.ll
…
thumb-big-stack.ll
…
thumb-litpool.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
thumb-stub.ll
…
tls1.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
tls2.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
tls3.ll
test: modernise ARM CodeGen tests
2016-12-27 18:35:19 +00:00
tls-models.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
trap.ll
…
trunc_ldr.ll
…
truncstore-dag-combine.ll
…
tst_teq.ll
…
twoaddrinstr.ll
…
uint64tof64.ll
…
umulo-32.ll
…
unaligned_load_store_vector.ll
…
unaligned_load_store_vfp.ll
…
unaligned_load_store.ll
…
undef-sext.ll
…
undefined.ll
…
unfold-shifts.ll
[ARM] and, or, xor and add with shl combine
2017-11-02 10:43:10 +00:00
unord.ll
…
unsafe-fsub.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
unschedule-first-call.ll
[ScheduleDAG] Don't schedule node with physical register interference
2017-08-01 00:28:40 +00:00
unwind-init.ll
…
urem-opt-size.ll
…
usat-lower.ll
…
usat-upper.ll
…
usat-v4t.ll
…
usat.ll
[ARM] Lower unsigned saturation to USAT
2017-12-20 11:13:57 +00:00
uxt_rot.ll
…
uxtb.ll
test: modernise ARM CodeGen tests
2016-12-27 18:35:19 +00:00
v1-constant-fold.ll
…
v6-jumptable-clobber.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
v6m-smul-with-overflow.ll
Fix signed multiplication with overflow fallback.
2017-04-26 13:41:43 +00:00
v6m-umul-with-overflow.ll
DAG: correctly legalize UMULO.
2017-06-20 15:01:38 +00:00
v7k-abi-align.ll
…
v7k-libcalls.ll
…
v7k-sincos.ll
…
v8m-tail-call.ll
[ARM] Accept a subset of Thumb GPR register class when emitting an SP-relative
2018-01-26 10:20:58 +00:00
v8m.base-jumptable_alignment.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
va_arg.ll
[ARM] Prefer BIC over BFC in ARM mode.
2017-04-07 22:01:23 +00:00
vaba.ll
…
vabd.ll
…
vabs.ll
[ARM][NEON] Add support for ISD::ABS lowering
2017-05-08 10:37:34 +00:00
vadd.ll
…
vararg_no_start.ll
…
varargs-spill-stack-align-nacl.ll
…
vargs_align.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
vargs.ll
…
vbits.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vbsl-constant.ll
…
vbsl.ll
…
vceq.ll
…
vcge.ll
…
vcgt.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
vcmp-crash.ll
[ARM] Fix crash caused by r294945
2017-02-13 17:18:00 +00:00
vcnt.ll
…
vcombine.ll
[DAGCombiner] use narrow load to avoid vector extract
2017-05-27 14:07:03 +00:00
vcvt_combine.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
vcvt-cost.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
vcvt-v8.ll
…
vcvt.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vdiv_combine.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
vdup.ll
DAG: Avoid OOB when legalizing vector indexing
2017-01-10 22:02:30 +00:00
vector-DAGCombine.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
vector-extend-narrow.ll
…
vector-load.ll
ARM: handle post-indexed NEON ops where the offset isn't the access width.
2017-04-20 19:54:02 +00:00
vector-promotion.ll
Don't conditionalize Neon instructions, even in IT blocks.
2017-06-22 12:11:38 +00:00
vector-spilling.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
vector-store.ll
ARM: handle post-indexed NEON ops where the offset isn't the access width.
2017-04-20 19:54:02 +00:00
vext.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vfcmp.ll
…
vfloatintrinsics.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
vfp-libcalls.ll
…
vfp-reg-stride.ll
…
vfp-regs-dwarf.ll
…
vfp.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
vget_lane.ll
…
vhadd.ll
…
vhsub.ll
…
vicmp-64.ll
…
vicmp.ll
…
virtregrewriter-subregliveness.mir
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
vld1.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
vld2.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
vld3.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
vld4.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
vld-vst-upgrade.ll
…
vlddup.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
vldlane.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
vldm-liveness.ll
[ARM] Check correct instructions for load/store rescheduling.
2017-03-01 22:56:20 +00:00
vldm-liveness.mir
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
vldm-sched-a9.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
vminmax.ll
…
vminmaxnm-safe.ll
…
vminmaxnm.ll
…
vmla.ll
…
vmls.ll
…
vmov.ll
…
vmul.ll
[ARM] Add ARMISD::VLD1DUP to match vld1_dup more consistently.
2016-12-16 18:44:08 +00:00
vneg.ll
…
vpadal.ll
…
vpadd.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vpminmax.ll
…
vqadd.ll
…
vqdmul.ll
…
vqshl.ll
…
vqshrn.ll
…
vqsub.ll
…
vrec.ll
…
vrev.ll
…
vsel.ll
[ARM] Use VCMP, not VCMPE, for floating point equality comparisons
2017-02-13 12:32:47 +00:00
vselect_imax.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00
vshift.ll
…
vshiftins.ll
…
vshl.ll
…
vshll.ll
[SelectionDAG] Teach simplifyDemandedBits to handle shifts by constant splat vectors
2017-09-25 19:26:08 +00:00
vshrn.ll
…
vsra.ll
…
vst1.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
vst2.ll
…
vst3.ll
…
vst4.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
vstlane.ll
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
2017-06-28 07:07:03 +00:00
vsub.ll
…
vtbl.ll
[ARM] Use TableGen patterns to select vtbl. NFC.
2017-04-19 20:39:39 +00:00
vtrn.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vuzp.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vzip.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
warn-stack.ll
…
weak2.ll
…
weak.ll
…
wide-compares.ll
[ARM] Avoid creating duplicate ANDs in SelectionDAG
2017-08-22 11:02:45 +00:00
widen-vmovs.ll
…
wrong-t2stmia-size-opt.ll
…
xray-armv6-attribute-instrumentation.ll
[XRay][CodeGen] Use PIC-friendly code in XRay sleds and remove synthetic references in .text
2017-09-04 05:34:58 +00:00
xray-armv7-attribute-instrumentation.ll
[XRay][CodeGen] Use PIC-friendly code in XRay sleds and remove synthetic references in .text
2017-09-04 05:34:58 +00:00
xray-tail-call-sled.ll
[xray] Add XRay support for Mach-O in CodeGen
2016-11-23 02:07:04 +00:00
zero-cycle-zero.ll
…
zextload_demandedbits.ll
ARM: Do not use llc -march in tests.
2017-08-01 22:20:49 +00:00