9427aa2d54
Summary: The maximum alignment used by ARM arch is 64bits, not 128. This could cause overaligned memory access for 128 bit neon vector that have unpredictable behaviour. This fixes: https://bugs.llvm.org/show_bug.cgi?id=42668 Reviewers: ostannard, dmgreen, srhines, danalbert, pirama, peter.smith Reviewed By: pirama, peter.smith Subscribers: phosek, thegameg, thakis, llvm-commits, carwil, peter.smith, javed.absar, kristof.beyls, cfe-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D65000 llvm-svn: 368288
22 lines
848 B
C++
22 lines
848 B
C++
// Bug: https://bugs.llvm.org/show_bug.cgi?id=42668
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// REQUIRES: arm-registered-target
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// RUN: %clang_cc1 -triple armv8-arm-none-eabi -emit-llvm -target-cpu generic -Os -fcxx-exceptions -o - -x c++ %s | FileCheck --check-prefixes=CHECK,A8 %s
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// RUN: %clang_cc1 -triple armv8-unknown-linux-android -emit-llvm -target-cpu generic -Os -fcxx-exceptions -o - -x c++ %s | FileCheck --check-prefixes=CHECK,A16 %s
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// CHECK: [[E:%[A-z0-9]+]] = tail call i8* @__cxa_allocate_exception
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// CHECK-NEXT: [[BC:%[A-z0-9]+]] = bitcast i8* [[E]] to <2 x i64>*
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// A8-NEXT: store <2 x i64> <i64 1, i64 2>, <2 x i64>* [[BC]], align 8
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// A16-NEXT: store <2 x i64> <i64 1, i64 2>, <2 x i64>* [[BC]], align 16
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#include <arm_neon.h>
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int main(void) {
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try {
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throw vld1q_u64(((const uint64_t[2]){1, 2}));
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} catch (uint64x2_t exc) {
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return 0;
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}
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return 1;
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}
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