4bb60c285c
This patch adds basic CSKY branch instructions and symbol address series instructions. Those two kinds of instruction have relationship between each other, and it involves much work about Fixups. For now, basic instructions are enabled except for disassembler support. We would support to generate basic codegen asm firstly and delay disassembler work later. Differential Revision: https://reviews.llvm.org/D95029
83 lines
2.9 KiB
C++
83 lines
2.9 KiB
C++
//===-- CSKYMCCodeEmitter.cpp - CSKY Code Emitter interface ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the CSKYMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#include "CSKYMCCodeEmitter.h"
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#include "MCTargetDesc/CSKYMCTargetDesc.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/Support/EndianStream.h"
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using namespace llvm;
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#define DEBUG_TYPE "csky-mccode-emitter"
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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unsigned CSKYMCCodeEmitter::getOImmOpValue(const MCInst &MI, unsigned Idx,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(Idx);
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assert(MO.isImm() && "Unexpected MO type.");
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return MO.getImm() - 1;
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}
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void CSKYMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCInstrDesc &Desc = MII.get(MI.getOpcode());
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unsigned Size = Desc.getSize();
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uint32_t Bin = getBinaryCodeForInstr(MI, Fixups, STI);
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uint16_t LO16 = static_cast<uint16_t>(Bin);
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uint16_t HI16 = static_cast<uint16_t>(Bin >> 16);
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if (Size == 4)
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support::endian::write<uint16_t>(OS, HI16, support::little);
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support::endian::write<uint16_t>(OS, LO16, support::little);
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++MCNumEmitted; // Keep track of the # of mi's emitted.
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}
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unsigned
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CSKYMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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if (MO.isReg())
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return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
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if (MO.isImm())
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return static_cast<unsigned>(MO.getImm());
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llvm_unreachable("Unhandled expression!");
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return 0;
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}
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MCFixupKind CSKYMCCodeEmitter::getTargetFixup(const MCExpr *Expr) const {
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const CSKYMCExpr *CSKYExpr = cast<CSKYMCExpr>(Expr);
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switch (CSKYExpr->getKind()) {
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default:
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llvm_unreachable("Unhandled fixup kind!");
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case CSKYMCExpr::VK_CSKY_ADDR:
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return MCFixupKind(CSKY::fixup_csky_addr32);
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}
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}
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MCCodeEmitter *llvm::createCSKYMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx) {
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return new CSKYMCCodeEmitter(Ctx, MCII);
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}
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#include "CSKYGenMCCodeEmitter.inc"
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