657bb7262d
Previously ADD & ADDA (as well as SUB & SUBA) instructions are mixed together, which not only violated Motorola assembly's syntax but also made asm parsing more difficult. This patch separates these two kinds of instructions migrate rest of the tests from test/CodeGen/M68k/Encoding/Arithmetic to test/MC/M68k/Arithmetic. Note that we observed minor regressions on codegen quality: Sometimes isel uses ADD instead of ADDA even the latter can lead to shorter sequence of code. This issue implies that some isel patterns might need to be updated.
897 lines
32 KiB
C++
897 lines
32 KiB
C++
//===-- M68kFrameLowering.cpp - M68k Frame Information ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file contains the M68k implementation of TargetFrameLowering class.
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///
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//===----------------------------------------------------------------------===//
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#include "M68kFrameLowering.h"
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#include "M68kInstrBuilder.h"
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#include "M68kInstrInfo.h"
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#include "M68kMachineFunction.h"
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#include "M68kSubtarget.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/Alignment.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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M68kFrameLowering::M68kFrameLowering(const M68kSubtarget &STI, Align Alignment)
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: TargetFrameLowering(StackGrowsDown, Alignment, -4), STI(STI),
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TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
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SlotSize = STI.getSlotSize();
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StackPtr = TRI->getStackRegister();
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}
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bool M68kFrameLowering::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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const TargetRegisterInfo *TRI = STI.getRegisterInfo();
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return MF.getTarget().Options.DisableFramePointerElim(MF) ||
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MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken() ||
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TRI->hasStackRealignment(MF);
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}
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// FIXME Make sure no other factors prevent us from reserving call frame
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bool M68kFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
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return !MF.getFrameInfo().hasVarSizedObjects() &&
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!MF.getInfo<M68kMachineFunctionInfo>()->getHasPushSequences();
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}
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bool M68kFrameLowering::canSimplifyCallFramePseudos(
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const MachineFunction &MF) const {
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return hasReservedCallFrame(MF) ||
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(hasFP(MF) && !TRI->hasStackRealignment(MF)) ||
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TRI->hasBasePointer(MF);
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}
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bool M68kFrameLowering::needsFrameIndexResolution(
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const MachineFunction &MF) const {
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return MF.getFrameInfo().hasStackObjects() ||
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MF.getInfo<M68kMachineFunctionInfo>()->getHasPushSequences();
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}
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// NOTE: this only has a subset of the full frame index logic. In
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// particular, the FI < 0 and AfterFPPop logic is handled in
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// M68kRegisterInfo::eliminateFrameIndex, but not here. Possibly
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// (probably?) it should be moved into here.
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StackOffset
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M68kFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
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Register &FrameReg) const {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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// We can't calculate offset from frame pointer if the stack is realigned,
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// so enforce usage of stack/base pointer. The base pointer is used when we
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// have dynamic allocas in addition to dynamic realignment.
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if (TRI->hasBasePointer(MF))
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FrameReg = TRI->getBaseRegister();
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else if (TRI->hasStackRealignment(MF))
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FrameReg = TRI->getStackRegister();
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else
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FrameReg = TRI->getFrameRegister(MF);
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// Offset will hold the offset from the stack pointer at function entry to the
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// object.
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// We need to factor in additional offsets applied during the prologue to the
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// frame, base, and stack pointer depending on which is used.
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int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea();
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const M68kMachineFunctionInfo *MMFI = MF.getInfo<M68kMachineFunctionInfo>();
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uint64_t StackSize = MFI.getStackSize();
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bool HasFP = hasFP(MF);
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// TODO: Support tail calls
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if (TRI->hasBasePointer(MF)) {
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assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
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if (FI < 0) {
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// Skip the saved FP.
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return StackOffset::getFixed(Offset + SlotSize);
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}
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assert((-(Offset + StackSize)) % MFI.getObjectAlign(FI).value() == 0);
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return StackOffset::getFixed(Offset + StackSize);
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}
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if (TRI->hasStackRealignment(MF)) {
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if (FI < 0) {
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// Skip the saved FP.
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return StackOffset::getFixed(Offset + SlotSize);
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}
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assert((-(Offset + StackSize)) % MFI.getObjectAlign(FI).value() == 0);
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return StackOffset::getFixed(Offset + StackSize);
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}
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if (!HasFP)
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return StackOffset::getFixed(Offset + StackSize);
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// Skip the saved FP.
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Offset += SlotSize;
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// Skip the RETADDR move area
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int TailCallReturnAddrDelta = MMFI->getTCReturnAddrDelta();
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if (TailCallReturnAddrDelta < 0)
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Offset -= TailCallReturnAddrDelta;
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return StackOffset::getFixed(Offset);
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}
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/// Return a caller-saved register that isn't live
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/// when it reaches the "return" instruction. We can then pop a stack object
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/// to this register without worry about clobbering it.
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static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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const M68kRegisterInfo *TRI) {
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const MachineFunction *MF = MBB.getParent();
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if (MF->callsEHReturn())
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return 0;
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const TargetRegisterClass &AvailableRegs = *TRI->getRegsForTailCall(*MF);
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if (MBBI == MBB.end())
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return 0;
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switch (MBBI->getOpcode()) {
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default:
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return 0;
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case TargetOpcode::PATCHABLE_RET:
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case M68k::RET: {
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SmallSet<uint16_t, 8> Uses;
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for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MBBI->getOperand(i);
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if (!MO.isReg() || MO.isDef())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
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Uses.insert(*AI);
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}
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for (auto CS : AvailableRegs)
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if (!Uses.count(CS))
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return CS;
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}
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}
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return 0;
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}
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static bool isRegLiveIn(MachineBasicBlock &MBB, unsigned Reg) {
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return llvm::any_of(MBB.liveins(),
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[Reg](MachineBasicBlock::RegisterMaskPair RegMask) {
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return RegMask.PhysReg == Reg;
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});
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}
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uint64_t
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M68kFrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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uint64_t MaxAlign = MFI.getMaxAlign().value(); // Desired stack alignment.
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unsigned StackAlign = getStackAlignment(); // ABI alignment
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if (MF.getFunction().hasFnAttribute("stackrealign")) {
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if (MFI.hasCalls())
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MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
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else if (MaxAlign < SlotSize)
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MaxAlign = SlotSize;
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}
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return MaxAlign;
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}
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void M68kFrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, unsigned Reg,
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uint64_t MaxAlign) const {
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uint64_t Val = -MaxAlign;
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unsigned AndOp = M68k::AND32di;
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unsigned MovOp = M68k::MOV32rr;
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// This function is normally used with SP which is Address Register, but AND,
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// or any other logical instructions in M68k do not support ARs so we need
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// to use a temp Data Register to perform the op.
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unsigned Tmp = M68k::D0;
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BuildMI(MBB, MBBI, DL, TII.get(MovOp), Tmp)
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.addReg(Reg)
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.setMIFlag(MachineInstr::FrameSetup);
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MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Tmp)
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.addReg(Tmp)
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.addImm(Val)
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.setMIFlag(MachineInstr::FrameSetup);
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// The CCR implicit def is dead.
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MI->getOperand(3).setIsDead();
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BuildMI(MBB, MBBI, DL, TII.get(MovOp), Reg)
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.addReg(Tmp)
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.setMIFlag(MachineInstr::FrameSetup);
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}
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MachineBasicBlock::iterator M68kFrameLowering::eliminateCallFramePseudoInstr(
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MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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bool ReserveCallFrame = hasReservedCallFrame(MF);
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unsigned Opcode = I->getOpcode();
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bool IsDestroy = Opcode == TII.getCallFrameDestroyOpcode();
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DebugLoc DL = I->getDebugLoc();
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uint64_t Amount = !ReserveCallFrame ? I->getOperand(0).getImm() : 0;
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uint64_t InternalAmt = (IsDestroy && Amount) ? I->getOperand(1).getImm() : 0;
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I = MBB.erase(I);
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if (!ReserveCallFrame) {
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// If the stack pointer can be changed after prologue, turn the
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// adjcallstackup instruction into a 'sub %SP, <amt>' and the
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// adjcallstackdown instruction into 'add %SP, <amt>'
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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unsigned StackAlign = getStackAlignment();
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Amount = alignTo(Amount, StackAlign);
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MachineModuleInfo &MMI = MF.getMMI();
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const auto &Fn = MF.getFunction();
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bool DwarfCFI = MMI.hasDebugInfo() || Fn.needsUnwindTableEntry();
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// If we have any exception handlers in this function, and we adjust
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// the SP before calls, we may need to indicate this to the unwinder
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// using GNU_ARGS_SIZE. Note that this may be necessary even when
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// Amount == 0, because the preceding function may have set a non-0
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// GNU_ARGS_SIZE.
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// TODO: We don't need to reset this between subsequent functions,
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// if it didn't change.
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bool HasDwarfEHHandlers = !MF.getLandingPads().empty();
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if (HasDwarfEHHandlers && !IsDestroy &&
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MF.getInfo<M68kMachineFunctionInfo>()->getHasPushSequences()) {
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BuildCFI(MBB, I, DL,
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MCCFIInstruction::createGnuArgsSize(nullptr, Amount));
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}
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if (Amount == 0)
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return I;
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// Factor out the amount that gets handled inside the sequence
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// (Pushes of argument for frame setup, callee pops for frame destroy)
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Amount -= InternalAmt;
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// TODO: This is needed only if we require precise CFA.
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// If this is a callee-pop calling convention, emit a CFA adjust for
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// the amount the callee popped.
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if (IsDestroy && InternalAmt && DwarfCFI && !hasFP(MF))
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BuildCFI(MBB, I, DL,
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MCCFIInstruction::createAdjustCfaOffset(nullptr, -InternalAmt));
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// Add Amount to SP to destroy a frame, or subtract to setup.
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int64_t StackAdjustment = IsDestroy ? Amount : -Amount;
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int64_t CfaAdjustment = -StackAdjustment;
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if (StackAdjustment) {
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// Merge with any previous or following adjustment instruction. Note: the
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// instructions merged with here do not have CFI, so their stack
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// adjustments do not feed into CfaAdjustment.
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StackAdjustment += mergeSPUpdates(MBB, I, true);
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StackAdjustment += mergeSPUpdates(MBB, I, false);
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if (StackAdjustment) {
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BuildStackAdjustment(MBB, I, DL, StackAdjustment, false);
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}
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}
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if (DwarfCFI && !hasFP(MF)) {
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// If we don't have FP, but need to generate unwind information,
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// we need to set the correct CFA offset after the stack adjustment.
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// How much we adjust the CFA offset depends on whether we're emitting
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// CFI only for EH purposes or for debugging. EH only requires the CFA
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// offset to be correct at each call site, while for debugging we want
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// it to be more precise.
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// TODO: When not using precise CFA, we also need to adjust for the
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// InternalAmt here.
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if (CfaAdjustment) {
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BuildCFI(
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MBB, I, DL,
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MCCFIInstruction::createAdjustCfaOffset(nullptr, CfaAdjustment));
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}
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}
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return I;
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}
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if (IsDestroy && InternalAmt) {
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// If we are performing frame pointer elimination and if the callee pops
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// something off the stack pointer, add it back. We do this until we have
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// more advanced stack pointer tracking ability.
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// We are not tracking the stack pointer adjustment by the callee, so make
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// sure we restore the stack pointer immediately after the call, there may
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// be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
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MachineBasicBlock::iterator CI = I;
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MachineBasicBlock::iterator B = MBB.begin();
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while (CI != B && !std::prev(CI)->isCall())
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--CI;
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BuildStackAdjustment(MBB, CI, DL, -InternalAmt, /*InEpilogue=*/false);
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}
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return I;
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}
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/// Emit a series of instructions to increment / decrement the stack pointer by
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/// a constant value.
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void M68kFrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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int64_t NumBytes, bool InEpilogue) const {
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bool IsSub = NumBytes < 0;
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uint64_t Offset = IsSub ? -NumBytes : NumBytes;
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uint64_t Chunk = (1LL << 31) - 1;
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DebugLoc DL = MBB.findDebugLoc(MBBI);
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while (Offset) {
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if (Offset > Chunk) {
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// Rather than emit a long series of instructions for large offsets,
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// load the offset into a register and do one sub/add
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Register Reg;
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if (IsSub && !isRegLiveIn(MBB, M68k::D0))
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Reg = M68k::D0;
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else
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Reg = findDeadCallerSavedReg(MBB, MBBI, TRI);
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if (Reg) {
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unsigned Opc = M68k::MOV32ri;
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BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg).addImm(Offset);
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Opc = IsSub ? M68k::SUB32ar : M68k::ADD32ar;
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MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
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.addReg(StackPtr)
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.addReg(Reg);
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// ??? still no CCR
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MI->getOperand(3).setIsDead(); // The CCR implicit def is dead.
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Offset = 0;
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continue;
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}
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}
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uint64_t ThisVal = std::min(Offset, Chunk);
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MachineInstrBuilder MI = BuildStackAdjustment(
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MBB, MBBI, DL, IsSub ? -ThisVal : ThisVal, InEpilogue);
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if (IsSub)
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MI.setMIFlag(MachineInstr::FrameSetup);
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else
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MI.setMIFlag(MachineInstr::FrameDestroy);
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Offset -= ThisVal;
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}
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}
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int M68kFrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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bool MergeWithPrevious) const {
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if ((MergeWithPrevious && MBBI == MBB.begin()) ||
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(!MergeWithPrevious && MBBI == MBB.end()))
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return 0;
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MachineBasicBlock::iterator PI = MergeWithPrevious ? std::prev(MBBI) : MBBI;
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MachineBasicBlock::iterator NI =
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MergeWithPrevious ? nullptr : std::next(MBBI);
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unsigned Opc = PI->getOpcode();
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int Offset = 0;
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if (!MergeWithPrevious && NI != MBB.end() &&
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NI->getOpcode() == TargetOpcode::CFI_INSTRUCTION) {
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// Don't merge with the next instruction if it has CFI.
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return Offset;
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}
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if (Opc == M68k::ADD32ai && PI->getOperand(0).getReg() == StackPtr) {
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assert(PI->getOperand(1).getReg() == StackPtr);
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Offset += PI->getOperand(2).getImm();
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MBB.erase(PI);
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if (!MergeWithPrevious)
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MBBI = NI;
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} else if (Opc == M68k::SUB32ai && PI->getOperand(0).getReg() == StackPtr) {
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assert(PI->getOperand(1).getReg() == StackPtr);
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Offset -= PI->getOperand(2).getImm();
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MBB.erase(PI);
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if (!MergeWithPrevious)
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MBBI = NI;
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}
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return Offset;
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}
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MachineInstrBuilder M68kFrameLowering::BuildStackAdjustment(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, int64_t Offset, bool InEpilogue) const {
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assert(Offset != 0 && "zero offset stack adjustment requested");
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// TODO can `lea` be used to adjust stack?
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bool IsSub = Offset < 0;
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uint64_t AbsOffset = IsSub ? -Offset : Offset;
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unsigned Opc = IsSub ? M68k::SUB32ai : M68k::ADD32ai;
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MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
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.addReg(StackPtr)
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.addImm(AbsOffset);
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// FIXME Update CCR as well. For now we just
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// conservatively say CCR implicit def is dead
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MI->getOperand(3).setIsDead();
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return MI;
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}
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void M68kFrameLowering::BuildCFI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL,
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const MCCFIInstruction &CFIInst) const {
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MachineFunction &MF = *MBB.getParent();
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unsigned CFIIndex = MF.addFrameInst(CFIInst);
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BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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void M68kFrameLowering::emitPrologueCalleeSavedFrameMoves(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL) const {
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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MachineModuleInfo &MMI = MF.getMMI();
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const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
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// Add callee saved registers to move list.
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const auto &CSI = MFI.getCalleeSavedInfo();
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if (CSI.empty())
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return;
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// Calculate offsets.
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for (const auto &I : CSI) {
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int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
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unsigned Reg = I.getReg();
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|
|
|
unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
|
|
BuildCFI(MBB, MBBI, DL,
|
|
MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
|
|
}
|
|
}
|
|
|
|
void M68kFrameLowering::emitPrologue(MachineFunction &MF,
|
|
MachineBasicBlock &MBB) const {
|
|
assert(&STI == &MF.getSubtarget<M68kSubtarget>() &&
|
|
"MF used frame lowering for wrong subtarget");
|
|
|
|
MachineBasicBlock::iterator MBBI = MBB.begin();
|
|
MachineFrameInfo &MFI = MF.getFrameInfo();
|
|
const auto &Fn = MF.getFunction();
|
|
MachineModuleInfo &MMI = MF.getMMI();
|
|
M68kMachineFunctionInfo *MMFI = MF.getInfo<M68kMachineFunctionInfo>();
|
|
uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
|
|
uint64_t StackSize = MFI.getStackSize(); // Number of bytes to allocate.
|
|
bool HasFP = hasFP(MF);
|
|
bool NeedsDwarfCFI = MMI.hasDebugInfo() || Fn.needsUnwindTableEntry();
|
|
unsigned FramePtr = TRI->getFrameRegister(MF);
|
|
const unsigned MachineFramePtr = FramePtr;
|
|
unsigned BasePtr = TRI->getBaseRegister();
|
|
|
|
// Debug location must be unknown since the first debug location is used
|
|
// to determine the end of the prologue.
|
|
DebugLoc DL;
|
|
|
|
// Add RETADDR move area to callee saved frame size.
|
|
int TailCallReturnAddrDelta = MMFI->getTCReturnAddrDelta();
|
|
|
|
if (TailCallReturnAddrDelta < 0) {
|
|
MMFI->setCalleeSavedFrameSize(MMFI->getCalleeSavedFrameSize() -
|
|
TailCallReturnAddrDelta);
|
|
}
|
|
|
|
// Insert stack pointer adjustment for later moving of return addr. Only
|
|
// applies to tail call optimized functions where the callee argument stack
|
|
// size is bigger than the callers.
|
|
if (TailCallReturnAddrDelta < 0) {
|
|
BuildStackAdjustment(MBB, MBBI, DL, TailCallReturnAddrDelta,
|
|
/*InEpilogue=*/false)
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
}
|
|
|
|
// Mapping for machine moves:
|
|
//
|
|
// DST: VirtualFP AND
|
|
// SRC: VirtualFP => DW_CFA_def_cfa_offset
|
|
// ELSE => DW_CFA_def_cfa
|
|
//
|
|
// SRC: VirtualFP AND
|
|
// DST: Register => DW_CFA_def_cfa_register
|
|
//
|
|
// ELSE
|
|
// OFFSET < 0 => DW_CFA_offset_extended_sf
|
|
// REG < 64 => DW_CFA_offset + Reg
|
|
// ELSE => DW_CFA_offset_extended
|
|
|
|
uint64_t NumBytes = 0;
|
|
int stackGrowth = -SlotSize;
|
|
|
|
if (HasFP) {
|
|
// Calculate required stack adjustment.
|
|
uint64_t FrameSize = StackSize - SlotSize;
|
|
// If required, include space for extra hidden slot for stashing base
|
|
// pointer.
|
|
if (MMFI->getRestoreBasePointer())
|
|
FrameSize += SlotSize;
|
|
|
|
NumBytes = FrameSize - MMFI->getCalleeSavedFrameSize();
|
|
|
|
// Callee-saved registers are pushed on stack before the stack is realigned.
|
|
if (TRI->hasStackRealignment(MF))
|
|
NumBytes = alignTo(NumBytes, MaxAlign);
|
|
|
|
// Get the offset of the stack slot for the FP register, which is
|
|
// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
|
|
// Update the frame offset adjustment.
|
|
MFI.setOffsetAdjustment(-NumBytes);
|
|
|
|
// Save FP into the appropriate stack slot.
|
|
BuildMI(MBB, MBBI, DL, TII.get(M68k::PUSH32r))
|
|
.addReg(MachineFramePtr, RegState::Kill)
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
|
|
if (NeedsDwarfCFI) {
|
|
// Mark the place where FP was saved.
|
|
// Define the current CFA rule to use the provided offset.
|
|
assert(StackSize);
|
|
BuildCFI(MBB, MBBI, DL,
|
|
MCCFIInstruction::cfiDefCfaOffset(nullptr, 2 * stackGrowth));
|
|
|
|
// Change the rule for the FramePtr to be an "offset" rule.
|
|
int DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
|
|
assert(DwarfFramePtr > 0);
|
|
BuildCFI(MBB, MBBI, DL,
|
|
MCCFIInstruction::createOffset(nullptr, DwarfFramePtr,
|
|
2 * stackGrowth));
|
|
}
|
|
|
|
// Update FP with the new base value.
|
|
BuildMI(MBB, MBBI, DL, TII.get(M68k::MOV32aa), FramePtr)
|
|
.addReg(StackPtr)
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
|
|
if (NeedsDwarfCFI) {
|
|
// Mark effective beginning of when frame pointer becomes valid.
|
|
// Define the current CFA to use the FP register.
|
|
unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
|
|
BuildCFI(MBB, MBBI, DL,
|
|
MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
|
|
}
|
|
|
|
// Mark the FramePtr as live-in in every block. Don't do this again for
|
|
// funclet prologues.
|
|
for (MachineBasicBlock &EveryMBB : MF)
|
|
EveryMBB.addLiveIn(MachineFramePtr);
|
|
} else {
|
|
NumBytes = StackSize - MMFI->getCalleeSavedFrameSize();
|
|
}
|
|
|
|
// Skip the callee-saved push instructions.
|
|
bool PushedRegs = false;
|
|
int StackOffset = 2 * stackGrowth;
|
|
|
|
while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup) &&
|
|
MBBI->getOpcode() == M68k::PUSH32r) {
|
|
PushedRegs = true;
|
|
++MBBI;
|
|
|
|
if (!HasFP && NeedsDwarfCFI) {
|
|
// Mark callee-saved push instruction.
|
|
// Define the current CFA rule to use the provided offset.
|
|
assert(StackSize);
|
|
BuildCFI(MBB, MBBI, DL,
|
|
MCCFIInstruction::cfiDefCfaOffset(nullptr, StackOffset));
|
|
StackOffset += stackGrowth;
|
|
}
|
|
}
|
|
|
|
// Realign stack after we pushed callee-saved registers (so that we'll be
|
|
// able to calculate their offsets from the frame pointer).
|
|
if (TRI->hasStackRealignment(MF)) {
|
|
assert(HasFP && "There should be a frame pointer if stack is realigned.");
|
|
BuildStackAlignAND(MBB, MBBI, DL, StackPtr, MaxAlign);
|
|
}
|
|
|
|
// If there is an SUB32ri of SP immediately before this instruction, merge
|
|
// the two. This can be the case when tail call elimination is enabled and
|
|
// the callee has more arguments then the caller.
|
|
NumBytes -= mergeSPUpdates(MBB, MBBI, true);
|
|
|
|
// Adjust stack pointer: ESP -= numbytes.
|
|
emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, /*InEpilogue=*/false);
|
|
|
|
unsigned SPOrEstablisher = StackPtr;
|
|
|
|
// If we need a base pointer, set it up here. It's whatever the value
|
|
// of the stack pointer is at this point. Any variable size objects
|
|
// will be allocated after this, so we can still use the base pointer
|
|
// to reference locals.
|
|
if (TRI->hasBasePointer(MF)) {
|
|
// Update the base pointer with the current stack pointer.
|
|
BuildMI(MBB, MBBI, DL, TII.get(M68k::MOV32aa), BasePtr)
|
|
.addReg(SPOrEstablisher)
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
if (MMFI->getRestoreBasePointer()) {
|
|
// Stash value of base pointer. Saving SP instead of FP shortens
|
|
// dependence chain. Used by SjLj EH.
|
|
unsigned Opm = M68k::MOV32ja;
|
|
M68k::addRegIndirectWithDisp(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
|
|
FramePtr, true,
|
|
MMFI->getRestoreBasePointerOffset())
|
|
.addReg(SPOrEstablisher)
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
}
|
|
}
|
|
|
|
if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
|
|
// Mark end of stack pointer adjustment.
|
|
if (!HasFP && NumBytes) {
|
|
// Define the current CFA rule to use the provided offset.
|
|
assert(StackSize);
|
|
BuildCFI(
|
|
MBB, MBBI, DL,
|
|
MCCFIInstruction::cfiDefCfaOffset(nullptr, -StackSize + stackGrowth));
|
|
}
|
|
|
|
// Emit DWARF info specifying the offsets of the callee-saved registers.
|
|
if (PushedRegs)
|
|
emitPrologueCalleeSavedFrameMoves(MBB, MBBI, DL);
|
|
}
|
|
|
|
// TODO Interrupt handlers
|
|
// M68k Interrupt handling function cannot assume anything about the
|
|
// direction flag (DF in CCR register). Clear this flag by creating "cld"
|
|
// instruction in each prologue of interrupt handler function. The "cld"
|
|
// instruction should only in these cases:
|
|
// 1. The interrupt handling function uses any of the "rep" instructions.
|
|
// 2. Interrupt handling function calls another function.
|
|
}
|
|
|
|
static bool isTailCallOpcode(unsigned Opc) {
|
|
return Opc == M68k::TCRETURNj || Opc == M68k::TCRETURNq;
|
|
}
|
|
|
|
void M68kFrameLowering::emitEpilogue(MachineFunction &MF,
|
|
MachineBasicBlock &MBB) const {
|
|
const MachineFrameInfo &MFI = MF.getFrameInfo();
|
|
M68kMachineFunctionInfo *MMFI = MF.getInfo<M68kMachineFunctionInfo>();
|
|
MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
|
|
Optional<unsigned> RetOpcode;
|
|
if (MBBI != MBB.end())
|
|
RetOpcode = MBBI->getOpcode();
|
|
DebugLoc DL;
|
|
if (MBBI != MBB.end())
|
|
DL = MBBI->getDebugLoc();
|
|
unsigned FramePtr = TRI->getFrameRegister(MF);
|
|
unsigned MachineFramePtr = FramePtr;
|
|
|
|
// Get the number of bytes to allocate from the FrameInfo.
|
|
uint64_t StackSize = MFI.getStackSize();
|
|
uint64_t MaxAlign = calculateMaxStackAlign(MF);
|
|
unsigned CSSize = MMFI->getCalleeSavedFrameSize();
|
|
uint64_t NumBytes = 0;
|
|
|
|
if (hasFP(MF)) {
|
|
// Calculate required stack adjustment.
|
|
uint64_t FrameSize = StackSize - SlotSize;
|
|
NumBytes = FrameSize - CSSize;
|
|
|
|
// Callee-saved registers were pushed on stack before the stack was
|
|
// realigned.
|
|
if (TRI->hasStackRealignment(MF))
|
|
NumBytes = alignTo(FrameSize, MaxAlign);
|
|
|
|
// Pop FP.
|
|
BuildMI(MBB, MBBI, DL, TII.get(M68k::POP32r), MachineFramePtr)
|
|
.setMIFlag(MachineInstr::FrameDestroy);
|
|
} else {
|
|
NumBytes = StackSize - CSSize;
|
|
}
|
|
|
|
// Skip the callee-saved pop instructions.
|
|
while (MBBI != MBB.begin()) {
|
|
MachineBasicBlock::iterator PI = std::prev(MBBI);
|
|
unsigned Opc = PI->getOpcode();
|
|
|
|
if ((Opc != M68k::POP32r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
|
|
Opc != M68k::DBG_VALUE && !PI->isTerminator())
|
|
break;
|
|
|
|
--MBBI;
|
|
}
|
|
MachineBasicBlock::iterator FirstCSPop = MBBI;
|
|
|
|
if (MBBI != MBB.end())
|
|
DL = MBBI->getDebugLoc();
|
|
|
|
// If there is an ADD32ri or SUB32ri of SP immediately before this
|
|
// instruction, merge the two instructions.
|
|
if (NumBytes || MFI.hasVarSizedObjects())
|
|
NumBytes += mergeSPUpdates(MBB, MBBI, true);
|
|
|
|
// If dynamic alloca is used, then reset SP to point to the last callee-saved
|
|
// slot before popping them off! Same applies for the case, when stack was
|
|
// realigned. Don't do this if this was a funclet epilogue, since the funclets
|
|
// will not do realignment or dynamic stack allocation.
|
|
if ((TRI->hasStackRealignment(MF) || MFI.hasVarSizedObjects())) {
|
|
if (TRI->hasStackRealignment(MF))
|
|
MBBI = FirstCSPop;
|
|
uint64_t LEAAmount = -CSSize;
|
|
|
|
// 'move %FramePtr, SP' will not be recognized as an epilogue sequence.
|
|
// However, we may use this sequence if we have a frame pointer because the
|
|
// effects of the prologue can safely be undone.
|
|
if (LEAAmount != 0) {
|
|
unsigned Opc = M68k::LEA32p;
|
|
M68k::addRegIndirectWithDisp(
|
|
BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr), FramePtr, false,
|
|
LEAAmount);
|
|
--MBBI;
|
|
} else {
|
|
unsigned Opc = (M68k::MOV32rr);
|
|
BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr).addReg(FramePtr);
|
|
--MBBI;
|
|
}
|
|
} else if (NumBytes) {
|
|
// Adjust stack pointer back: SP += numbytes.
|
|
emitSPUpdate(MBB, MBBI, NumBytes, /*InEpilogue=*/true);
|
|
--MBBI;
|
|
}
|
|
|
|
if (!RetOpcode || !isTailCallOpcode(*RetOpcode)) {
|
|
// Add the return addr area delta back since we are not tail calling.
|
|
int Offset = -1 * MMFI->getTCReturnAddrDelta();
|
|
assert(Offset >= 0 && "TCDelta should never be positive");
|
|
if (Offset) {
|
|
MBBI = MBB.getFirstTerminator();
|
|
|
|
// Check for possible merge with preceding ADD instruction.
|
|
Offset += mergeSPUpdates(MBB, MBBI, true);
|
|
emitSPUpdate(MBB, MBBI, Offset, /*InEpilogue=*/true);
|
|
}
|
|
}
|
|
}
|
|
|
|
void M68kFrameLowering::determineCalleeSaves(MachineFunction &MF,
|
|
BitVector &SavedRegs,
|
|
RegScavenger *RS) const {
|
|
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
|
|
|
|
MachineFrameInfo &MFI = MF.getFrameInfo();
|
|
|
|
M68kMachineFunctionInfo *M68kFI = MF.getInfo<M68kMachineFunctionInfo>();
|
|
int64_t TailCallReturnAddrDelta = M68kFI->getTCReturnAddrDelta();
|
|
|
|
if (TailCallReturnAddrDelta < 0) {
|
|
// create RETURNADDR area
|
|
// arg
|
|
// arg
|
|
// RETADDR
|
|
// { ...
|
|
// RETADDR area
|
|
// ...
|
|
// }
|
|
// [FP]
|
|
MFI.CreateFixedObject(-TailCallReturnAddrDelta,
|
|
TailCallReturnAddrDelta - SlotSize, true);
|
|
}
|
|
|
|
// Spill the BasePtr if it's used.
|
|
if (TRI->hasBasePointer(MF)) {
|
|
SavedRegs.set(TRI->getBaseRegister());
|
|
}
|
|
}
|
|
|
|
bool M68kFrameLowering::assignCalleeSavedSpillSlots(
|
|
MachineFunction &MF, const TargetRegisterInfo *TRI,
|
|
std::vector<CalleeSavedInfo> &CSI) const {
|
|
MachineFrameInfo &MFI = MF.getFrameInfo();
|
|
M68kMachineFunctionInfo *M68kFI = MF.getInfo<M68kMachineFunctionInfo>();
|
|
|
|
int SpillSlotOffset = getOffsetOfLocalArea() + M68kFI->getTCReturnAddrDelta();
|
|
|
|
if (hasFP(MF)) {
|
|
// emitPrologue always spills frame register the first thing.
|
|
SpillSlotOffset -= SlotSize;
|
|
MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
|
|
|
|
// Since emitPrologue and emitEpilogue will handle spilling and restoring of
|
|
// the frame register, we can delete it from CSI list and not have to worry
|
|
// about avoiding it later.
|
|
unsigned FPReg = TRI->getFrameRegister(MF);
|
|
for (unsigned i = 0, e = CSI.size(); i < e; ++i) {
|
|
if (TRI->regsOverlap(CSI[i].getReg(), FPReg)) {
|
|
CSI.erase(CSI.begin() + i);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
// The rest is fine
|
|
return false;
|
|
}
|
|
|
|
bool M68kFrameLowering::spillCalleeSavedRegisters(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
|
ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
|
|
auto &MRI = *static_cast<const M68kRegisterInfo *>(TRI);
|
|
auto DL = MBB.findDebugLoc(MI);
|
|
|
|
int FI = 0;
|
|
unsigned Mask = 0;
|
|
for (const auto &Info : CSI) {
|
|
FI = std::max(FI, Info.getFrameIdx());
|
|
unsigned Reg = Info.getReg();
|
|
unsigned Shift = MRI.getSpillRegisterOrder(Reg);
|
|
Mask |= 1 << Shift;
|
|
}
|
|
|
|
auto I =
|
|
M68k::addFrameReference(BuildMI(MBB, MI, DL, TII.get(M68k::MOVM32pm)), FI)
|
|
.addImm(Mask)
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
|
|
// Append implicit registers and mem locations
|
|
const MachineFunction &MF = *MBB.getParent();
|
|
const MachineRegisterInfo &RI = MF.getRegInfo();
|
|
for (const auto &Info : CSI) {
|
|
unsigned Reg = Info.getReg();
|
|
bool IsLiveIn = RI.isLiveIn(Reg);
|
|
if (!IsLiveIn)
|
|
MBB.addLiveIn(Reg);
|
|
I.addReg(Reg, IsLiveIn ? RegState::Implicit : RegState::ImplicitKill);
|
|
M68k::addMemOperand(I, Info.getFrameIdx(), 0);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool M68kFrameLowering::restoreCalleeSavedRegisters(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
|
MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
|
|
auto &MRI = *static_cast<const M68kRegisterInfo *>(TRI);
|
|
auto DL = MBB.findDebugLoc(MI);
|
|
|
|
int FI = 0;
|
|
unsigned Mask = 0;
|
|
for (const auto &Info : CSI) {
|
|
FI = std::max(FI, Info.getFrameIdx());
|
|
unsigned Reg = Info.getReg();
|
|
unsigned Shift = MRI.getSpillRegisterOrder(Reg);
|
|
Mask |= 1 << Shift;
|
|
}
|
|
|
|
auto I = M68k::addFrameReference(
|
|
BuildMI(MBB, MI, DL, TII.get(M68k::MOVM32mp)).addImm(Mask), FI)
|
|
.setMIFlag(MachineInstr::FrameDestroy);
|
|
|
|
// Append implicit registers and mem locations
|
|
for (const auto &Info : CSI) {
|
|
I.addReg(Info.getReg(), RegState::ImplicitDefine);
|
|
M68k::addMemOperand(I, Info.getFrameIdx(), 0);
|
|
}
|
|
|
|
return true;
|
|
}
|