When writing a unit test on replacing standard epilogue sequences with `BR __mspabi_func_epilog_<N>`, by manually asm-clobbering `rN` - `r10` for N = 4..10, everything worked well except for seeming inability to clobber r4. The problem was that MSP430 code generator of LLVM used an obsolete name FP for that register. Things were worse because when `llc` read an unknown register name, it silently ignored it. That is, I cannot use `fp` register name from the C code because Clang does not accept it (exactly like GCC). But the accepted name `r4` is not recognised by `llc` (it can be used in listings passed to `llvm-mc` and even `fp` is replace to `r4` by `llvm-mc`). So I can specify any of `fp` or `r4` for the string literal of `asm(...)` but nothing in the clobber list. This patch replaces `MSP430::FP` with `MSP430::R4` in the backend code (even [MSP430 EABI](http://www.ti.com/lit/an/slaa534/slaa534.pdf) doesn't mention FP as a register name). The R0 - R3 registers, on the other hand, are left as is in the backend code (after all, they have some special meaning on the ISA level). It is just ensured clang is renaming them as expected by the downstream tools. There is probably not much sense in **marking them clobbered** but rename them //just in case// for use at potentially different contexts. Differential Revision: https://reviews.llvm.org/D82184
294 lines
10 KiB
C++
294 lines
10 KiB
C++
//===-- MSP430FrameLowering.cpp - MSP430 Frame Information ----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MSP430 implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "MSP430FrameLowering.h"
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#include "MSP430InstrInfo.h"
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#include "MSP430MachineFunctionInfo.h"
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#include "MSP430Subtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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bool MSP430FrameLowering::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
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MF.getFrameInfo().hasVarSizedObjects() ||
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MFI.isFrameAddressTaken());
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}
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bool MSP430FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
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return !MF.getFrameInfo().hasVarSizedObjects();
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}
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void MSP430FrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
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MachineFrameInfo &MFI = MF.getFrameInfo();
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MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
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const MSP430InstrInfo &TII =
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*static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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// Get the number of bytes to allocate from the FrameInfo.
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uint64_t StackSize = MFI.getStackSize();
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uint64_t NumBytes = 0;
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if (hasFP(MF)) {
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// Calculate required stack adjustment
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uint64_t FrameSize = StackSize - 2;
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NumBytes = FrameSize - MSP430FI->getCalleeSavedFrameSize();
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// Get the offset of the stack slot for the EBP register... which is
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// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
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// Update the frame offset adjustment.
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MFI.setOffsetAdjustment(-NumBytes);
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// Save FP into the appropriate stack slot...
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
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.addReg(MSP430::R4, RegState::Kill);
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// Update FP with the new base value...
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::R4)
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.addReg(MSP430::SP);
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// Mark the FramePtr as live-in in every block except the entry.
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for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
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I != E; ++I)
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I->addLiveIn(MSP430::R4);
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} else
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NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize();
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// Skip the callee-saved push instructions.
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while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r))
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++MBBI;
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if (MBBI != MBB.end())
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DL = MBBI->getDebugLoc();
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if (NumBytes) { // adjust stack pointer: SP -= numbytes
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// If there is an SUB16ri of SP immediately before this instruction, merge
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// the two.
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//NumBytes -= mergeSPUpdates(MBB, MBBI, true);
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// If there is an ADD16ri or SUB16ri of SP immediately after this
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// instruction, merge the two instructions.
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// mergeSPUpdatesDown(MBB, MBBI, &NumBytes);
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if (NumBytes) {
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MachineInstr *MI =
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP)
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.addReg(MSP430::SP).addImm(NumBytes);
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// The SRW implicit def is dead.
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MI->getOperand(3).setIsDead();
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}
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}
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}
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void MSP430FrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
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const MSP430InstrInfo &TII =
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*static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo());
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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unsigned RetOpcode = MBBI->getOpcode();
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DebugLoc DL = MBBI->getDebugLoc();
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switch (RetOpcode) {
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case MSP430::RET:
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case MSP430::RETI: break; // These are ok
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default:
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llvm_unreachable("Can only insert epilog into returning blocks");
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}
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// Get the number of bytes to allocate from the FrameInfo
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uint64_t StackSize = MFI.getStackSize();
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unsigned CSSize = MSP430FI->getCalleeSavedFrameSize();
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uint64_t NumBytes = 0;
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if (hasFP(MF)) {
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// Calculate required stack adjustment
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uint64_t FrameSize = StackSize - 2;
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NumBytes = FrameSize - CSSize;
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// pop FP.
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::R4);
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} else
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NumBytes = StackSize - CSSize;
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// Skip the callee-saved pop instructions.
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while (MBBI != MBB.begin()) {
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MachineBasicBlock::iterator PI = std::prev(MBBI);
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unsigned Opc = PI->getOpcode();
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if (Opc != MSP430::POP16r && !PI->isTerminator())
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break;
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--MBBI;
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}
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DL = MBBI->getDebugLoc();
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// If there is an ADD16ri or SUB16ri of SP immediately before this
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// instruction, merge the two instructions.
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//if (NumBytes || MFI.hasVarSizedObjects())
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// mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
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if (MFI.hasVarSizedObjects()) {
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BuildMI(MBB, MBBI, DL,
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TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::R4);
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if (CSSize) {
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MachineInstr *MI =
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BuildMI(MBB, MBBI, DL,
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TII.get(MSP430::SUB16ri), MSP430::SP)
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.addReg(MSP430::SP).addImm(CSSize);
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// The SRW implicit def is dead.
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MI->getOperand(3).setIsDead();
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}
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} else {
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// adjust stack pointer back: SP += numbytes
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if (NumBytes) {
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MachineInstr *MI =
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP)
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.addReg(MSP430::SP).addImm(NumBytes);
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// The SRW implicit def is dead.
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MI->getOperand(3).setIsDead();
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}
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}
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}
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// FIXME: Can we eleminate these in favour of generic code?
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bool MSP430FrameLowering::spillCalleeSavedRegisters(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
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if (CSI.empty())
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return false;
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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MSP430MachineFunctionInfo *MFI = MF.getInfo<MSP430MachineFunctionInfo>();
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MFI->setCalleeSavedFrameSize(CSI.size() * 2);
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for (unsigned i = CSI.size(); i != 0; --i) {
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unsigned Reg = CSI[i-1].getReg();
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// Add the callee-saved register as live-in. It's killed at the spill.
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MBB.addLiveIn(Reg);
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BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r))
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.addReg(Reg, RegState::Kill);
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}
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return true;
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}
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bool MSP430FrameLowering::restoreCalleeSavedRegisters(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
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if (CSI.empty())
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return false;
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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for (unsigned i = 0, e = CSI.size(); i != e; ++i)
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BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());
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return true;
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}
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MachineBasicBlock::iterator MSP430FrameLowering::eliminateCallFramePseudoInstr(
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MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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const MSP430InstrInfo &TII =
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*static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo());
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if (!hasReservedCallFrame(MF)) {
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// If the stack pointer can be changed after prologue, turn the
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// adjcallstackup instruction into a 'sub SP, <amt>' and the
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// adjcallstackdown instruction into 'add SP, <amt>'
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// TODO: consider using push / pop instead of sub + store / add
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MachineInstr &Old = *I;
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uint64_t Amount = TII.getFrameSize(Old);
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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Amount = alignTo(Amount, getStackAlign());
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MachineInstr *New = nullptr;
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if (Old.getOpcode() == TII.getCallFrameSetupOpcode()) {
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New =
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BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::SUB16ri), MSP430::SP)
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.addReg(MSP430::SP)
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.addImm(Amount);
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} else {
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assert(Old.getOpcode() == TII.getCallFrameDestroyOpcode());
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// factor out the amount the callee already popped.
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Amount -= TII.getFramePoppedByCallee(Old);
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if (Amount)
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New = BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::ADD16ri),
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MSP430::SP)
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.addReg(MSP430::SP)
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.addImm(Amount);
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}
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if (New) {
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// The SRW implicit def is dead.
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New->getOperand(3).setIsDead();
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// Replace the pseudo instruction with a new instruction...
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MBB.insert(I, New);
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}
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}
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} else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) {
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// If we are performing frame pointer elimination and if the callee pops
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// something off the stack pointer, add it back.
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if (uint64_t CalleeAmt = TII.getFramePoppedByCallee(*I)) {
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MachineInstr &Old = *I;
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MachineInstr *New =
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BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::SUB16ri), MSP430::SP)
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.addReg(MSP430::SP)
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.addImm(CalleeAmt);
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// The SRW implicit def is dead.
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New->getOperand(3).setIsDead();
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MBB.insert(I, New);
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}
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}
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return MBB.erase(I);
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}
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void
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MSP430FrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
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RegScavenger *) const {
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// Create a frame entry for the FP register that must be saved.
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if (hasFP(MF)) {
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int FrameIdx = MF.getFrameInfo().CreateFixedObject(2, -4, true);
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(void)FrameIdx;
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assert(FrameIdx == MF.getFrameInfo().getObjectIndexBegin() &&
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"Slot for FP register must be last in order to be found!");
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}
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}
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