81efb82570
If we need to shift left anyway we might be able to take advantage of LUI implicitly shifting its immediate left by 12 to cover part of the shift. This allows us to use more bits of the LUI immediate to avoid an ADDI. isDesirableToCommuteWithShift now considers compressed instruction opportunities when deciding if commuting should be allowed. I believe this is the same or similar to one of the optimizations from D79492. Reviewed By: luismarques, arcbbb Differential Revision: https://reviews.llvm.org/D105417
52 lines
1.9 KiB
C++
52 lines
1.9 KiB
C++
//===- RISCVMatInt.h - Immediate materialisation ---------------*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MATINT_H
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#define LLVM_LIB_TARGET_RISCV_MATINT_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include <cstdint>
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namespace llvm {
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class APInt;
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class MCSubtargetInfo;
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namespace RISCVMatInt {
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struct Inst {
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unsigned Opc;
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int64_t Imm;
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Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {}
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};
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using InstSeq = SmallVector<Inst, 8>;
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// Helper to generate an instruction sequence that will materialise the given
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// immediate value into a register. A sequence of instructions represented by a
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// simple struct is produced rather than directly emitting the instructions in
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// order to allow this helper to be used from both the MC layer and during
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// instruction selection.
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InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures);
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// Helper to estimate the number of instructions required to materialise the
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// given immediate value into a register. This estimate does not account for
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// `Val` possibly fitting into an immediate, and so may over-estimate.
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//
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// This will attempt to produce instructions to materialise `Val` as an
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// `Size`-bit immediate.
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//
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// If CompressionCost is true it will use a different cost calculation if RVC is
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// enabled. This should be used to compare two different sequences to determine
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// which is more compressible.
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int getIntMatCost(const APInt &Val, unsigned Size,
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const FeatureBitset &ActiveFeatures,
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bool CompressionCost = false);
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} // namespace RISCVMatInt
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} // namespace llvm
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#endif
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