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clang-p2996/llvm/lib/Target/VE
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Kazushi (Jam) Marukawa 4ee28b4fec [VE] Set getExtendForAtomicOps to ISD::ANY_EXTEND 
The implementation of subword atomics does not actually
guarantee the result is zero-extended, which now caused
failures after https://reviews.llvm.org/D101342 was landed.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D106225
2021-07-19 19:58:44 +09:00
..
AsmParser
…
Disassembler
…
MCTargetDesc
[VE] Add include for formatted_raw_ostream after 046cfb8565
2021-01-29 11:18:30 -08:00
TargetInfo
…
CMakeLists.txt
…
LVLGen.cpp
[VE] Correct LVLGen (LVL instruction insert pass)
2020-12-09 06:33:53 +09:00
VE.h
[VE] Change inetger constants 32-bit friendly
2021-02-01 19:00:47 +09:00
VE.td
[VE] Change default CPU name to "generic"
2021-01-04 20:09:57 +09:00
VEAsmPrinter.cpp
[VE][NFC] Update comments to match the generated instructions
2021-01-07 15:13:24 +09:00
VECallingConv.td
[VE] Correct VMP allocation in calling conv
2020-12-21 22:42:24 +09:00
VEFrameLowering.cpp
[NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions
2021-03-30 17:31:39 +01:00
VEFrameLowering.h
[VE] Optimize prologue/epilogue instructions
2020-11-30 22:22:33 +09:00
VEInstrBuilder.h
[VE] Support SJLJ exception related instructions
2021-01-05 20:19:15 +09:00
VEInstrFormats.td
[VE] Add VBRD/VMV instructions
2020-10-19 18:33:54 +09:00
VEInstrInfo.cpp
[VE] Support copy of vector mask registers
2020-12-19 09:16:43 +09:00
VEInstrInfo.h
…
VEInstrInfo.td
[VE] Fix types of multiclass template arguments in TableGen files
2021-03-20 10:36:51 -07:00
VEInstrIntrinsicVL.gen.td
[VE] Add logical mask intrinsic instructions
2020-12-15 01:34:31 +09:00
VEInstrIntrinsicVL.td
[VE] Support additional VMRGW and VMV intrinsic instructions
2021-01-11 20:50:31 +09:00
VEInstrPatternsVec.td
[VE] Fix types of multiclass template arguments in TableGen files
2021-03-20 10:36:51 -07:00
VEInstrVec.td
[VE] Add logical mask intrinsic instructions
2020-12-15 01:34:31 +09:00
VEISelDAGToDAG.cpp
[llvm] Use isa instead of dyn_cast (NFC)
2021-01-29 23:23:37 -08:00
VEISelLowering.cpp
[VE][NFC] IRBuilder<> -> IRBuilderBase
2021-06-08 13:55:49 +02:00
VEISelLowering.h
[VE] Set getExtendForAtomicOps to ISD::ANY_EXTEND
2021-07-19 19:58:44 +09:00
VEMachineFunctionInfo.cpp
[VE] call isel with stack passing
2020-01-28 10:55:47 +01:00
VEMachineFunctionInfo.h
[VE] Support for PIC (global data and calls)
2020-02-14 09:50:02 +01:00
VEMCInstLower.cpp
[VE] Implement JumpTable
2020-11-17 22:43:10 +09:00
VERegisterInfo.cpp
[VE] Support atomic exchange instructions
2020-12-15 17:43:11 +09:00
VERegisterInfo.h
…
VERegisterInfo.td
…
VESubtarget.cpp
[VE] Change default CPU name to "generic"
2021-01-04 20:09:57 +09:00
VESubtarget.h
…
VETargetMachine.cpp
[llvm] Use Optional::getValueOr (NFC)
2021-01-12 21:43:50 -08:00
VETargetMachine.h
[VE] Target-specific bit size for sjljehprepare
2020-03-10 17:51:16 +01:00
VETargetTransformInfo.h
[VE] Disable relative lookup table converter pass for VE
2021-07-19 19:25:33 +09:00
VVPInstrInfo.td
[VE] Vector 'and' isel and tests
2020-12-23 13:29:29 +01:00
VVPInstrPatternsVec.td
[VE] Vector 'and' isel and tests
2020-12-23 13:29:29 +01:00
VVPNodes.def
[VP] ISD helper functions [VE] isel for vp_add, vp_and
2021-01-08 14:29:45 +01:00