129388ddc4
Summary: The estimation uses AMDGPUTargetLowering::isFNegFree() Reviewers: rampitec Reviewed By: rampitec Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D82065
103 lines
4.0 KiB
LLVM
103 lines
4.0 KiB
LLVM
; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
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; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
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; CHECK-LABEL: 'fneg_f32'
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; CHECK: estimated cost of 0 for instruction: %fneg = fneg float
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define amdgpu_kernel void @fneg_f32(float addrspace(1)* %out, float addrspace(1)* %vaddr) {
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%vec = load float, float addrspace(1)* %vaddr
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%fadd = fadd float %vec, undef
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%fneg = fneg float %fadd
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store float %fneg, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: 'fneg_v2f32'
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; CHECK: estimated cost of 0 for instruction: %fneg = fneg <2 x float>
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define amdgpu_kernel void @fneg_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %vaddr) {
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%vec = load <2 x float>, <2 x float> addrspace(1)* %vaddr
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%fadd = fadd <2 x float> %vec, undef
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%fneg = fneg <2 x float> %fadd
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store <2 x float> %fneg, <2 x float> addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: 'fneg_v3f32'
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; CHECK: estimated cost of 0 for instruction: %fneg = fneg <3 x float>
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define amdgpu_kernel void @fneg_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %vaddr) {
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%vec = load <3 x float>, <3 x float> addrspace(1)* %vaddr
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%fadd = fadd <3 x float> %vec, undef
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%fneg = fneg <3 x float> %fadd
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store <3 x float> %fneg, <3 x float> addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: 'fneg_v5f32'
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; CHECK: estimated cost of 0 for instruction: %fneg = fneg <5 x float>
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define amdgpu_kernel void @fneg_v5f32(<5 x float> addrspace(1)* %out, <5 x float> addrspace(1)* %vaddr) {
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%vec = load <5 x float>, <5 x float> addrspace(1)* %vaddr
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%fadd = fadd <5 x float> %vec, undef
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%fneg = fneg <5 x float> %fadd
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store <5 x float> %fneg, <5 x float> addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: 'fneg_f64'
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; CHECK: estimated cost of 0 for instruction: %fneg = fneg double
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define amdgpu_kernel void @fneg_f64(double addrspace(1)* %out, double addrspace(1)* %vaddr) {
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%vec = load double, double addrspace(1)* %vaddr
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%fadd = fadd double %vec, undef
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%fneg = fneg double %fadd
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store double %fneg, double addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: 'fneg_v2f64'
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; CHECK: estimated cost of 0 for instruction: %fneg = fneg <2 x double>
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define amdgpu_kernel void @fneg_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %vaddr) {
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%vec = load <2 x double>, <2 x double> addrspace(1)* %vaddr
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%fadd = fadd <2 x double> %vec, undef
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%fneg = fneg <2 x double> %fadd
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store <2 x double> %fneg, <2 x double> addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: 'fneg_v3f64'
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; CHECK: estimated cost of 0 for instruction: %fneg = fneg <3 x double>
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define amdgpu_kernel void @fneg_v3f64(<3 x double> addrspace(1)* %out, <3 x double> addrspace(1)* %vaddr) {
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%vec = load <3 x double>, <3 x double> addrspace(1)* %vaddr
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%fadd = fadd <3 x double> %vec, undef
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%fneg = fneg <3 x double> %fadd
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store <3 x double> %fneg, <3 x double> addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: 'fneg_f16'
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; CHECK: estimated cost of 0 for instruction: %fneg = fneg half
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define amdgpu_kernel void @fneg_f16(half addrspace(1)* %out, half addrspace(1)* %vaddr) {
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%vec = load half, half addrspace(1)* %vaddr
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%fadd = fadd half %vec, undef
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%fneg = fneg half %fadd
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store half %fneg, half addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: 'fneg_v2f16'
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; CHECK: estimated cost of 0 for instruction: %fneg = fneg <2 x half>
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define amdgpu_kernel void @fneg_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %vaddr) {
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%vec = load <2 x half>, <2 x half> addrspace(1)* %vaddr
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%fadd = fadd <2 x half> %vec, undef
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%fneg = fneg <2 x half> %fadd
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store <2 x half> %fneg, <2 x half> addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: 'fneg_v3f16'
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; CHECK: estimated cost of 0 for instruction: %fneg = fneg <3 x half>
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define amdgpu_kernel void @fneg_v3f16(<3 x half> addrspace(1)* %out, <3 x half> addrspace(1)* %vaddr) {
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%vec = load <3 x half>, <3 x half> addrspace(1)* %vaddr
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%fadd = fadd <3 x half> %vec, undef
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%fneg = fneg <3 x half> %fadd
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store <3 x half> %fneg, <3 x half> addrspace(1)* %out
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ret void
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}
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