2596da3174
Have BasicTTI call the base implementation so that both agree on the default behaviour, which the default being a cost of '1'. This has required an X86 specific implementation as it seems to be very reliant on those instructions being free. Changes are also made to AMDGPU so that their implementations distinguish between cost kinds, so that the unrolling isn't affected. PowerPC also has its own implementation to prevent changes to the reg-usage vectorizer test. The cost model test changes now reflect that ret instructions are not generally free. Differential Revision: https://reviews.llvm.org/D79164
28 lines
1.3 KiB
LLVM
28 lines
1.3 KiB
LLVM
; RUN: opt < %s -cost-model -analyze -mtriple=systemz-unknown -mcpu=z13 | FileCheck %s
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;
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; Test costs for i8 and i16 comparisons against memory with a small immediate.
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define i32 @fun0(i8* %Src, i8* %Dst, i8 %Val) {
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; CHECK: Printing analysis 'Cost Model Analysis' for function 'fun0':
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; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %Ld = load i8, i8* %Src
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; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %Cmp = icmp eq i8 %Ld, 123
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; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %Ret = zext i1 %Cmp to i32
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; CHECK: Cost Model: Found an estimated cost of 1 for instruction: ret i32 %Ret
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%Ld = load i8, i8* %Src
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%Cmp = icmp eq i8 %Ld, 123
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%Ret = zext i1 %Cmp to i32
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ret i32 %Ret
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}
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define i32 @fun1(i16* %Src, i16* %Dst, i16 %Val) {
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; CHECK: Printing analysis 'Cost Model Analysis' for function 'fun1':
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; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %Ld = load i16, i16* %Src
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; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %Cmp = icmp eq i16
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; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %Ret = zext i1 %Cmp to i32
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; CHECK: Cost Model: Found an estimated cost of 1 for instruction: ret i32 %Ret
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%Ld = load i16, i16* %Src
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%Cmp = icmp eq i16 %Ld, 1234
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%Ret = zext i1 %Cmp to i32
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ret i32 %Ret
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}
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