fae05692a3
This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
83 lines
4.0 KiB
LLVM
83 lines
4.0 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=instruction-select < %s | FileCheck %s
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declare void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float>, <4 x float>, i64, float*)
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declare void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, i64, float*)
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declare void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, i64, float*)
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define void @addstx(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
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%al = load <4 x float>, <4 x float>* %a
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%bl = load <4 x float>, <4 x float>* %b
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%cl = load <4 x float>, <4 x float>* %c
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%dl = load <4 x float>, <4 x float>* %d
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%ar = fadd <4 x float> %al, %bl
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%br = fadd <4 x float> %bl, %cl
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%cr = fadd <4 x float> %cl, %dl
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%dr = fadd <4 x float> %dl, %al
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; The sizes below are conservative. AArch64TargetLowering
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; conservatively assumes the entire vector is stored.
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tail call void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, float* %res)
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; CHECK: ST2Twov4s {{.*}} :: (store (s256) {{.*}})
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tail call void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, float* %res)
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; CHECK: ST3Threev4s {{.*}} :: (store (s384) {{.*}})
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tail call void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, float* %res)
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; CHECK: ST4Fourv4s {{.*}} :: (store (s512) {{.*}})
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ret void
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}
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define void @addst1x(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
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%al = load <4 x float>, <4 x float>* %a
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%bl = load <4 x float>, <4 x float>* %b
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%cl = load <4 x float>, <4 x float>* %c
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%dl = load <4 x float>, <4 x float>* %d
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%ar = fadd <4 x float> %al, %bl
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%br = fadd <4 x float> %bl, %cl
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%cr = fadd <4 x float> %cl, %dl
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%dr = fadd <4 x float> %dl, %al
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; The sizes below are conservative. AArch64TargetLowering
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; conservatively assumes the entire vector is stored.
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tail call void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, float* %res)
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; CHECK: ST1Twov4s {{.*}} :: (store (s256) {{.*}})
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tail call void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, float* %res)
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; CHECK: ST1Threev4s {{.*}} :: (store (s384) {{.*}})
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tail call void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, float* %res)
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; CHECK: ST1Fourv4s {{.*}} :: (store (s512) {{.*}})
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ret void
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}
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define void @addstxlane(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
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%al = load <4 x float>, <4 x float>* %a
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%bl = load <4 x float>, <4 x float>* %b
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%cl = load <4 x float>, <4 x float>* %c
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%dl = load <4 x float>, <4 x float>* %d
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%ar = fadd <4 x float> %al, %bl
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%br = fadd <4 x float> %bl, %cl
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%cr = fadd <4 x float> %cl, %dl
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%dr = fadd <4 x float> %dl, %al
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; The sizes below are conservative. AArch64TargetLowering
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; conservatively assumes the entire vector is stored.
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tail call void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, i64 1, float* %res)
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; CHECK: ST2i32 {{.*}} :: (store (s256) {{.*}})
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tail call void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, i64 1, float* %res)
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; CHECK: ST3i32 {{.*}} :: (store (s384) {{.*}})
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tail call void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, i64 1, float* %res)
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; CHECK: ST4i32 {{.*}} :: (store (s512) {{.*}})
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ret void
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}
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