322d0afd87
This change renames the intrinsics to not have "experimental" in the name. The autoupgrader will handle legacy intrinsics. Relevant ML thread: http://lists.llvm.org/pipermail/llvm-dev/2020-April/140729.html Differential Revision: https://reviews.llvm.org/D88787
32 lines
1.2 KiB
LLVM
32 lines
1.2 KiB
LLVM
; REQUIRES: arm-registered-target
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; REQUIRES: asserts
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; RUN: llc -o /dev/null %s -debug-only=legalize-types 2>&1 | FileCheck %s
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; This test check that when v4f64 gets broken down to two v2f64 it maintains
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; the "nnan" flags.
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; CHECK: Legalizing node: [[VFOUR:t.*]]: v4f64 = BUILD_VECTOR
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; CHECK-NEXT: Analyzing result type: v4f64
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; CHECK-NEXT: Split node result: [[VFOUR]]: v4f64 = BUILD_VECTOR
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; CHECK: Legalizing node: [[VTWO:t.*]]: v2f64 = BUILD_VECTOR
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; CHECK: Legally typed node: [[VTWO]]: v2f64 = BUILD_VECTOR
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; CHECK: Legalizing node: t26: v2f64 = fmaxnum nnan reassoc [[VTWO]], [[VTWO]]
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--linux-gnu"
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; Function Attrs: norecurse nounwind
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define fastcc double @test() unnamed_addr #1 {
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entry:
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%0 = insertelement <4 x double> undef, double 1.0, i32 0
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%1 = insertelement <4 x double> %0, double 1.0, i32 1
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%2 = insertelement <4 x double> %1, double 1.0, i32 2
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%3 = insertelement <4 x double> %2, double 1.0, i32 3
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%4 = call nnan reassoc double @llvm.vector.reduce.fmax.v4f64(<4 x double> %3)
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ret double %4
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}
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declare double @llvm.vector.reduce.fmax.v4f64(<4 x double>)
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