f9f5d41545
Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
113 lines
3.5 KiB
LLVM
113 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - < %s | FileCheck --check-prefix=GCN %s
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - < %s | FileCheck --check-prefix=GCN %s
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - < %s | FileCheck --check-prefix=GFX10 %s
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; Test vector bitfield extract.
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define i32 @v_srl_mask_i32(i32 %value) {
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; GCN-LABEL: v_srl_mask_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_bfe_u32 v0, v0, 8, 5
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: v_srl_mask_i32:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: v_bfe_u32 v0, v0, 8, 5
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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%1 = lshr i32 %value, 8
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%2 = and i32 %1, 31
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ret i32 %2
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}
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; Test scalar bitfield extract.
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define amdgpu_ps i32 @s_srl_mask_i32(i32 inreg %value) {
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; GCN-LABEL: s_srl_mask_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_bfe_u32 s0, s0, 0x50008
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; GCN-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: s_srl_mask_i32:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_bfe_u32 s0, s0, 0x50008
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; GFX10-NEXT: ; return to shader part epilog
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%1 = lshr i32 %value, 8
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%2 = and i32 %1, 31
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ret i32 %2
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}
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; Don't generate G_UBFX if the offset + width is too big.
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define amdgpu_ps i32 @s_srl_big_mask_i32(i32 inreg %value) {
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; GCN-LABEL: s_srl_big_mask_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_lshr_b32 s0, s0, 30
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; GCN-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: s_srl_big_mask_i32:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_lshr_b32 s0, s0, 30
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; GFX10-NEXT: ; return to shader part epilog
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%1 = lshr i32 %value, 30
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%2 = and i32 %1, 31
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ret i32 %2
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}
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; Test vector bitfield extract for 64-bits.
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define i64 @v_srl_mask_i64(i64 %value) {
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; GCN-LABEL: v_srl_mask_i64:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_lshrrev_b64 v[0:1], 25, v[0:1]
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: v_bfe_u32 v0, v0, 0, 10
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: v_srl_mask_i64:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: v_lshrrev_b64 v[0:1], 25, v[0:1]
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: v_bfe_u32 v0, v0, 0, 10
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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%1 = lshr i64 %value, 25
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%2 = and i64 %1, 1023
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ret i64 %2
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}
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; Test scalar bitfield extract for 64-bits.
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define amdgpu_ps i64 @s_srl_mask_i64(i64 inreg %value) {
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; GCN-LABEL: s_srl_mask_i64:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_bfe_u64 s[0:1], s[0:1], 0xa0019
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; GCN-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: s_srl_mask_i64:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_bfe_u64 s[0:1], s[0:1], 0xa0019
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; GFX10-NEXT: ; return to shader part epilog
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%1 = lshr i64 %value, 25
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%2 = and i64 %1, 1023
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ret i64 %2
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}
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; Don't generate G_UBFX if the offset + width is too big.
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define amdgpu_ps i64 @s_srl_big_mask_i64(i64 inreg %value) {
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; GCN-LABEL: s_srl_big_mask_i64:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_lshr_b32 s0, s1, 28
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; GCN-NEXT: s_mov_b32 s1, 0
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; GCN-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: s_srl_big_mask_i64:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_lshr_b32 s0, s1, 28
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; GFX10-NEXT: s_mov_b32 s1, 0
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; GFX10-NEXT: ; return to shader part epilog
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%1 = lshr i64 %value, 60
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%2 = and i64 %1, 63
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ret i64 %2
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}
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