eebe841a47
AMDGPU normally spills SGPRs to VGPRs. Previously, since all register classes are handled at the same time, this was problematic. We don't know ahead of time how many registers will be needed to be reserved to handle the spilling. If no VGPRs were left for spilling, we would have to try to spill to memory. If the spilled SGPRs were required for exec mask manipulation, it is highly problematic because the lanes active at the point of spill are not necessarily the same as at the restore point. Avoid this problem by fully allocating SGPRs in a separate regalloc run from VGPRs. This way we know the exact number of VGPRs needed, and can reserve them for a second run. This fixes the most serious issues, but it is still possible using inline asm to make all VGPRs unavailable. Start erroring in the case where we ever would require memory for an SGPR spill. This is implemented by giving each regalloc pass a callback which reports if a register class should be handled or not. A few passes need some small changes to deal with leftover virtual registers. In the AMDGPU implementation, a new pass is introduced to take the place of PrologEpilogInserter for SGPR spills emitted during the first run. One disadvantage of this is currently StackSlotColoring is no longer used for SGPR spills. It would need to be run again, which will require more work. Error if the standard -regalloc option is used. Introduce new separate -sgpr-regalloc and -vgpr-regalloc flags, so the two runs can be controlled individually. PBQB is not currently supported, so this also prevents using the unhandled allocator.
211 lines
6.3 KiB
LLVM
211 lines
6.3 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX90A %s
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; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX908 %s
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; GCN-LABEL: {{^}}func_empty:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GCN: s_setpc_b64
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define void @func_empty() #0 {
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ret void
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}
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; GCN-LABEL: {{^}}func_areg_4:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GCN: use agpr3
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GCN: s_setpc_b64
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define void @func_areg_4() #0 {
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call void asm sideeffect "; use agpr3", "~{a3}" ()
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ret void
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}
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; GCN-LABEL: {{^}}func_areg_32:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GCN: use agpr31
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GCN: s_setpc_b64
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define void @func_areg_32() #0 {
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call void asm sideeffect "; use agpr31", "~{a31}" ()
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ret void
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}
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; GCN-LABEL: {{^}}func_areg_33:
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; GCN-NOT: a32
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; GFX90A: v_accvgpr_read_b32 v0, a32 ; Reload Reuse
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; GCN-NOT: a32
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; GCN: use agpr32
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; GCN-NOT: a32
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; GFX90A: v_accvgpr_write_b32 a32, v0 ; Reload Reuse
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; GCN-NOT: a32
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; GCN: s_setpc_b64
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define void @func_areg_33() #0 {
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call void asm sideeffect "; use agpr32", "~{a32}" ()
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ret void
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}
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; GCN-LABEL: {{^}}func_areg_64:
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; GFX908-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GFX90A: v_accvgpr_read_b32 v0, a63 ; Reload Reuse
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; GCN: use agpr63
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; GFX90A: v_accvgpr_write_b32 a63, v0 ; Reload Reuse
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; GCN-NOT: v_accvgpr
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; GCN: s_setpc_b64
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define void @func_areg_64() #0 {
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call void asm sideeffect "; use agpr63", "~{a63}" ()
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ret void
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}
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; GCN-LABEL: {{^}}func_areg_31_63:
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; GFX908-NOT: buffer_
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; GFX908-NOT: v_accvgpr
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; GFX908-NOT: buffer
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; GFX90A: v_accvgpr_read_b32 v0, a63 ; Reload Reuse
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; GCN: use agpr31, agpr63
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; GFX90A: v_accvgpr_write_b32 a63, v0 ; Reload Reuse
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; GFX908-NOT: v_accvgpr
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; GFX908-NOT: buffer
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; GCN: s_setpc_b64
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define void @func_areg_31_63() #0 {
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call void asm sideeffect "; use agpr31, agpr63", "~{a31},~{a63}" ()
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ret void
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}
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declare void @func_unknown() #0
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; GCN-LABEL: {{^}}test_call_empty:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GCN: def a[0:31]
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; GFX908-COUNT-8: v_accvgpr_read_b32
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; GFX90A-NOT: v_accvgpr
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; GCN-NOT: buffer_
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_
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; GFX90A-NOT: v_accvgpr
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; GFX908-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], v[{{[0-9:]+}}]
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; GFX90A-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], a[{{[0-9:]+}}]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_call_empty() #0 {
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bb:
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%reg = call <32 x float> asm sideeffect "; def $0", "=a"()
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call void @func_empty()
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store volatile <32 x float> %reg, <32 x float> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_call_areg4:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GFX908: def a[0:31]
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; GFX90A: def a[4:35]
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; GFX908-COUNT-8: v_accvgpr_read_b32
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; GFX90A-NOT: v_accvgpr
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; GCN-NOT: buffer_
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_
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; GFX90A-NOT: v_accvgpr
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; GFX908-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], v[{{[0-9:]+}}]
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; GFX90A-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], a[{{[0-9:]+}}]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_call_areg4() #0 {
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bb:
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%reg = call <32 x float> asm sideeffect "; def $0", "=a"()
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call void @func_areg_4()
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store volatile <32 x float> %reg, <32 x float> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_call_areg32:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GFX908: def a[0:31]
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; GFX90A: def a[32:63]
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; GFX908-COUNT-8: v_accvgpr_read_b32
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; GFX90A-NOT: v_accvgpr
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; GCN-NOT: buffer_
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_
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; GFX90A-NOT: v_accvgpr
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; GFX908-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], v[{{[0-9:]+}}]
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; GFX90A-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], a[{{[0-9:]+}}]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_call_areg32() #0 {
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bb:
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%reg = call <32 x float> asm sideeffect "; def $0", "=a"()
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call void @func_areg_32()
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store volatile <32 x float> %reg, <32 x float> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_call_areg64:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GCN: def a[0:31]
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; GFX908-COUNT-8: v_accvgpr_read_b32
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; GFX90A-NOT: v_accvgpr
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; GCN-NOT: buffer_
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_
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; GFX90A-NOT: v_accvgpr
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; GFX908-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], v[{{[0-9:]+}}]
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; GFX90A-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], a[{{[0-9:]+}}]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_call_areg64() #0 {
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bb:
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%reg = call <32 x float> asm sideeffect "; def $0", "=a"()
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call void @func_areg_64()
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store volatile <32 x float> %reg, <32 x float> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_call_areg31_63:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GFX908: def a[0:31]
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; GFX90A: def a[32:63]
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; GFX908-COUNT-8: v_accvgpr_read_b32
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; GFX90A-NOT: v_accvgpr
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; GCN-NOT: buffer_
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_
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; GFX90A-NOT: v_accvgpr
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; GFX908-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], v[{{[0-9:]+}}]
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; GFX90A-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], a[{{[0-9:]+}}]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_call_areg31_63() #0 {
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bb:
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%reg = call <32 x float> asm sideeffect "; def $0", "=a"()
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call void @func_areg_31_63()
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store volatile <32 x float> %reg, <32 x float> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_call_unknown:
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; GCN-NOT: buffer_
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; GCN-NOT: v_accvgpr
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; GFX908: def a[0:31]
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; GFX90A: def a[32:63]
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; GFX908-COUNT-8: v_accvgpr_read_b32
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; GFX90A-NOT: v_accvgpr
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; GCN-NOT: buffer_
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_
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; GFX90A-NOT: v_accvgpr
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; GFX908-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], v[{{[0-9:]+}}]
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; GFX90A-COUNT-8: global_store_dwordx4 v[{{[0-9:]+}}], a[{{[0-9:]+}}]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_call_unknown() #0 {
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bb:
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%reg = call <32 x float> asm sideeffect "; def $0", "=a"()
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call void @func_unknown()
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store volatile <32 x float> %reg, <32 x float> addrspace(1)* undef
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ret void
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}
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attributes #0 = { nounwind noinline "amdgpu-flat-work-group-size"="1,512" }
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