3bffb1cd0e
Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469
49 lines
1.3 KiB
YAML
49 lines
1.3 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=si-fold-operands,dead-mi-elimination -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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---
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# GCN-LABEL: name: fold_sgpr_to_sgpr_copy_full
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# GCN: %0:sgpr_32 = IMPLICIT_DEF
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# GCN-NEXT: S_STORE_DWORD_IMM %0, undef $sgpr10_sgpr11, 0, 0
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name: fold_sgpr_to_sgpr_copy_full
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body: |
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bb.0:
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%0:sgpr_32 = IMPLICIT_DEF
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%1:sgpr_32 = COPY %0
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%2:sgpr_32 = COPY %1
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S_STORE_DWORD_IMM %2, undef $sgpr10_sgpr11, 0, 0
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...
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# GCN-LABEL: name: fold_sgpr_to_sgpr_copy_subreg
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# GCN: %0:sreg_64 = IMPLICIT_DEF
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# GCN-NEXT: %2:sgpr_32 = COPY %0.sub0
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# GCN-NEXT: S_STORE_DWORD_IMM %2, undef $sgpr10_sgpr11, 0, 0
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name: fold_sgpr_to_sgpr_copy_subreg
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body: |
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bb.0:
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%0:sreg_64 = IMPLICIT_DEF
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%1:sgpr_32 = COPY %0.sub0
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%2:sgpr_32 = COPY %1
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S_STORE_DWORD_IMM %2, undef $sgpr10_sgpr11, 0, 0
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...
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# GCN-LABEL: name: fold_sgpr_to_sgpr_copy_subreg2
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# GCN: %0:sreg_64 = IMPLICIT_DEF
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# GCN-NEXT: %3:sreg_32_xm0_xexec = COPY %0.sub0
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# GCN-NEXT: S_STORE_DWORD_IMM %3, undef $sgpr10_sgpr11, 0, 0
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name: fold_sgpr_to_sgpr_copy_subreg2
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body: |
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bb.0:
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%0:sreg_64 = IMPLICIT_DEF
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%1:sgpr_32 = COPY %0.sub0
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%2:sgpr_32 = COPY %1
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%3:sreg_32_xm0_xexec = COPY %2
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S_STORE_DWORD_IMM %3, undef $sgpr10_sgpr11, 0, 0
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...
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