ed0f4415f0
Description: This change enables the compare operations to be selected to SALU/VALU form
dependent of the SDNode divergence flag.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D106079
96 lines
2.9 KiB
LLVM
96 lines
2.9 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
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; GCN-LABEL: {{^}}test_i64_eq:
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; VI: s_cmp_eq_u64
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; SI: v_cmp_eq_u64
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define amdgpu_kernel void @test_i64_eq(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp eq i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_i64_ne:
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; VI: s_cmp_lg_u64
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; SI: v_cmp_ne_u64
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define amdgpu_kernel void @test_i64_ne(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp ne i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_i64_slt:
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; GCN: v_cmp_lt_i64
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define amdgpu_kernel void @test_i64_slt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp slt i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_i64_ult:
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; GCN: v_cmp_lt_u64
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define amdgpu_kernel void @test_i64_ult(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp ult i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_i64_sle:
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; GCN: v_cmp_le_i64
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define amdgpu_kernel void @test_i64_sle(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp sle i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_i64_ule:
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; GCN: v_cmp_le_u64
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define amdgpu_kernel void @test_i64_ule(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp ule i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_i64_sgt:
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; GCN: v_cmp_gt_i64
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define amdgpu_kernel void @test_i64_sgt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp sgt i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_i64_ugt:
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; GCN: v_cmp_gt_u64
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define amdgpu_kernel void @test_i64_ugt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp ugt i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_i64_sge:
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; GCN: v_cmp_ge_i64
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define amdgpu_kernel void @test_i64_sge(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp sge i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_i64_uge:
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; GCN: v_cmp_ge_u64
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define amdgpu_kernel void @test_i64_uge(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp uge i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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