fae05692a3
This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
156 lines
5.4 KiB
YAML
156 lines
5.4 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck %s
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# The purpose of this test is to make sure we are combining relevant memory
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# operations correctly with/without SCC bit.
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--- |
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define amdgpu_kernel void @test1(i32 addrspace(1)* %out) {
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%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
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store i32 123, i32 addrspace(1)* %out.gep.1
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store i32 456, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @test2(i32 addrspace(1)* %out) {
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%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
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store i32 123, i32 addrspace(1)* %out.gep.1
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store i32 456, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @test3(i32 addrspace(1)* %out) {
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%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
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store i32 123, i32 addrspace(1)* %out.gep.1
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store i32 456, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @test4(i32 addrspace(1)* %out) {
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%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
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store i32 123, i32 addrspace(1)* %out.gep.1
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store i32 456, i32 addrspace(1)* %out
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ret void
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}
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...
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# CHECK: BUFFER_STORE_DWORDX2_OFFSET killed %{{[0-9]+}}, %{{[0-9]+}}, 0, 4, 0, 0, 0, implicit $exec :: (store (s64) into %ir.out.gep.1, align 4, addrspace 1)
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---
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name: test1
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liveins:
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- { reg: '$sgpr0_sgpr1', virtual-reg: '' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $sgpr0_sgpr1
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$vgpr0 = V_MOV_B32_e32 123, implicit $exec
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$vgpr1 = V_MOV_B32_e32 456, implicit $exec
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$sgpr2 = S_MOV_B32 -1
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$sgpr3 = S_MOV_B32 61440
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sgpr_64 = S_LOAD_DWORDX2_IMM %1, 36, 0 :: (dereferenceable invariant load (s64) from `i64 addrspace(4)* undef`, addrspace 4)
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%2:sgpr_32 = COPY $sgpr2
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%3:sgpr_32 = COPY $sgpr3
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%4:sgpr_128 = REG_SEQUENCE %1, %2, %3
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%5:vgpr_32 = COPY $vgpr0
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%6:vgpr_32 = COPY $vgpr1
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BUFFER_STORE_DWORD_OFFSET %5, %4, 0, 4, 0, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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BUFFER_STORE_DWORD_OFFSET %6, %4, 0, 8, 0, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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S_ENDPGM 0
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...
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# CHECK: BUFFER_STORE_DWORD_OFFSET %{{[0-9]+}}, %{{[0-9]+}}, 0, 4, 16, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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# CHECK: BUFFER_STORE_DWORD_OFFSET %{{[0-9]+}}, %{{[0-9]+}}, 0, 8, 0, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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---
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name: test2
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liveins:
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- { reg: '$sgpr0_sgpr1', virtual-reg: '' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $sgpr0_sgpr1
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$vgpr0 = V_MOV_B32_e32 123, implicit $exec
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$vgpr1 = V_MOV_B32_e32 456, implicit $exec
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$sgpr2 = S_MOV_B32 -1
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$sgpr3 = S_MOV_B32 61440
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sgpr_64 = S_LOAD_DWORDX2_IMM %1, 36, 0 :: (dereferenceable invariant load (s64) from `i64 addrspace(4)* undef`, addrspace 4)
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%2:sgpr_32 = COPY $sgpr2
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%3:sgpr_32 = COPY $sgpr3
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%4:sgpr_128 = REG_SEQUENCE %1, %2, %3
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%5:vgpr_32 = COPY $vgpr0
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%6:vgpr_32 = COPY $vgpr1
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BUFFER_STORE_DWORD_OFFSET %5, %4, 0, 4, 16, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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BUFFER_STORE_DWORD_OFFSET %6, %4, 0, 8, 0, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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S_ENDPGM 0
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...
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# CHECK: BUFFER_STORE_DWORD_OFFSET %{{[0-9]+}}, %{{[0-9]+}}, 0, 4, 0, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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# CHECK: BUFFER_STORE_DWORD_OFFSET %{{[0-9]+}}, %{{[0-9]+}}, 0, 8, 16, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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---
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name: test3
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liveins:
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- { reg: '$sgpr0_sgpr1', virtual-reg: '' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $sgpr0_sgpr1
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$vgpr0 = V_MOV_B32_e32 123, implicit $exec
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$vgpr1 = V_MOV_B32_e32 456, implicit $exec
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$sgpr2 = S_MOV_B32 -1
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$sgpr3 = S_MOV_B32 61440
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sgpr_64 = S_LOAD_DWORDX2_IMM %1, 36, 0 :: (dereferenceable invariant load (s64) from `i64 addrspace(4)* undef`, addrspace 4)
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%2:sgpr_32 = COPY $sgpr2
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%3:sgpr_32 = COPY $sgpr3
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%4:sgpr_128 = REG_SEQUENCE %1, %2, %3
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%5:vgpr_32 = COPY $vgpr0
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%6:vgpr_32 = COPY $vgpr1
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BUFFER_STORE_DWORD_OFFSET %5, %4, 0, 4, 0, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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BUFFER_STORE_DWORD_OFFSET %6, %4, 0, 8, 16, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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S_ENDPGM 0
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...
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# CHECK: BUFFER_STORE_DWORDX2_OFFSET killed %{{[0-9]+}}, %{{[0-9]+}}, 0, 4, 16, 0, 0, implicit $exec :: (store (s64) into %ir.out.gep.1, align 4, addrspace 1)
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---
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name: test4
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liveins:
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- { reg: '$sgpr0_sgpr1', virtual-reg: '' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $sgpr0_sgpr1
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$vgpr0 = V_MOV_B32_e32 123, implicit $exec
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$vgpr1 = V_MOV_B32_e32 456, implicit $exec
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$sgpr2 = S_MOV_B32 -1
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$sgpr3 = S_MOV_B32 61440
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sgpr_64 = S_LOAD_DWORDX2_IMM %1, 36, 0 :: (dereferenceable invariant load (s64) from `i64 addrspace(4)* undef`, addrspace 4)
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%2:sgpr_32 = COPY $sgpr2
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%3:sgpr_32 = COPY $sgpr3
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%4:sgpr_128 = REG_SEQUENCE %1, %2, %3
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%5:vgpr_32 = COPY $vgpr0
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%6:vgpr_32 = COPY $vgpr1
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BUFFER_STORE_DWORD_OFFSET %5, %4, 0, 4, 16, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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BUFFER_STORE_DWORD_OFFSET %6, %4, 0, 8, 16, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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S_ENDPGM 0
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...
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