fe5f4c397f
Pass no longer handles skips. Pass now removes unnecessary unconditional branches and lowers early termination branches. Hence rename to SILateBranchLowering. Move code to handle returns to epilog from SIPreEmitPeephole into SILateBranchLowering. This means SIPreEmitPeephole only contains optional optimisations, and all required transforms are in SILateBranchLowering. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D98915
102 lines
2.8 KiB
YAML
102 lines
2.8 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -start-before si-shrink-instructions -stop-before si-late-branch-lowering -o - %s | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: subbrev{{$}}
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# GCN: V_SUBBREV_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec
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---
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name: subbrev
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_64_xexec }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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%3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
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%4, %5 = V_SUBBREV_U32_e64 0, %0, %3, 0, implicit $exec
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GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: subb{{$}}
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# GCN: V_SUBBREV_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec
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---
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name: subb
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_64_xexec }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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%3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
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%4, %5 = V_SUBB_U32_e64 %0, 0, %3, 0, implicit $exec
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GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: addc{{$}}
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# GCN: V_ADDC_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec
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---
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name: addc
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_64_xexec }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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%3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
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%4, %5 = V_ADDC_U32_e64 0, %0, %3, 0, implicit $exec
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GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: addc2{{$}}
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# GCN: V_ADDC_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec
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---
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name: addc2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_64_xexec }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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%3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
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%4, %5 = V_ADDC_U32_e64 %0, 0, %3, 0, implicit $exec
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GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec
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...
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