d2e52eec51
Use the 64-bit SGPR base with a 0 offset, since it's 1 fewer instruction to materialize the 0 vs. the 64-bit copy.
30 lines
1.0 KiB
LLVM
30 lines
1.0 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
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; GCN-LABEL: ; %bb.0:
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; GCN: s_load_dword s{{[0-9]+}}, s{{\[}}[[ADDR_LO:[0-9]+]]{{\:}}[[ADDR_HI:[0-9]+]]{{\]}}, 0x0
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; GCN: s_waitcnt lgkmcnt(0)
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; GCN: global_store_dword v
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define amdgpu_kernel void @zot(i32 addrspace(1)* nocapture %arg, i64 addrspace(1)* nocapture %arg1) {
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bb:
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%tmp = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp2 = icmp eq i32 %tmp, 0
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br i1 %tmp2, label %bb3, label %bb8
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bb3: ; preds = %bb
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%tmp4 = load i32, i32 addrspace(1)* %arg, align 4
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store i32 0, i32 addrspace(1)* %arg, align 4
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%tmp5 = zext i32 %tmp4 to i64
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%tmp6 = load i64, i64 addrspace(1)* %arg1, align 8
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%tmp7 = add i64 %tmp6, %tmp5
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store i64 %tmp7, i64 addrspace(1)* %arg1, align 8
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br label %bb8
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bb8: ; preds = %bb3, %bb
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ret void
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}
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; Function Attrs: nounwind readnone speculatable
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone speculatable }
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