40202b13b2
These instructions have an implicit use of vcc which counts towards the constant bus limit. Pre gfx10 this means that the explicit operands cannot be sgprs. Use the custom inserter hook to call legalizeOperands to enforce that restriction. Fixes https://bugs.llvm.org/show_bug.cgi?id=51217 Differential Revision: https://reviews.llvm.org/D106868
246 lines
9.3 KiB
LLVM
246 lines
9.3 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
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; FUNC-LABEL: {{^}}s_uaddo_i64_zext:
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; GCN: s_add_u32
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; GCN: s_addc_u32
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; GCN: v_cmp_lt_u64_e32 vcc
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; EG: ADDC_UINT
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; EG: ADDC_UINT
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define amdgpu_kernel void @s_uaddo_i64_zext(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 {
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%uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue { i64, i1 } %uadd, 0
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%carry = extractvalue { i64, i1 } %uadd, 1
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%ext = zext i1 %carry to i64
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%add2 = add i64 %val, %ext
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store i64 %add2, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FIXME: Could do scalar
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; FUNC-LABEL: {{^}}s_uaddo_i32:
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; SI: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
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; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
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; EG: ADDC_UINT
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; EG: ADD_INT
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define amdgpu_kernel void @s_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) #0 {
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%uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue { i32, i1 } %uadd, 0
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%carry = extractvalue { i32, i1 } %uadd, 1
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_uaddo_i32:
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; SI: v_add_i32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
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; EG: ADDC_UINT
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; EG: ADD_INT
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define amdgpu_kernel void @v_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %a.ptr, i32 addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr
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%b.gep = getelementptr inbounds i32, i32 addrspace(1)* %b.ptr
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%a = load i32, i32 addrspace(1)* %a.gep, align 4
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%b = load i32, i32 addrspace(1)* %b.gep, align 4
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%uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue { i32, i1 } %uadd, 0
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%carry = extractvalue { i32, i1 } %uadd, 1
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_uaddo_i32_novcc:
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; SI: v_add_i32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
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; EG: ADDC_UINT
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; EG: ADD_INT
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define amdgpu_kernel void @v_uaddo_i32_novcc(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %a.ptr, i32 addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr
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%b.gep = getelementptr inbounds i32, i32 addrspace(1)* %b.ptr
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%a = load i32, i32 addrspace(1)* %a.gep, align 4
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%b = load i32, i32 addrspace(1)* %b.gep, align 4
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%uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue { i32, i1 } %uadd, 0
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%carry = extractvalue { i32, i1 } %uadd, 1
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store volatile i32 %val, i32 addrspace(1)* %out, align 4
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call void asm sideeffect "", "~{vcc}"() #0
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store volatile i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}s_uaddo_i64:
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; GCN: s_add_u32
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; GCN: s_addc_u32
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; EG: ADDC_UINT
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; EG: ADD_INT
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define amdgpu_kernel void @s_uaddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a, i64 %b) #0 {
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%uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue { i64, i1 } %uadd, 0
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%carry = extractvalue { i64, i1 } %uadd, 1
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store i64 %val, i64 addrspace(1)* %out, align 8
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_uaddo_i64:
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; SI: v_add_i32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; SI: v_addc_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_addc_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc,
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; EG: ADDC_UINT
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; EG: ADD_INT
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define amdgpu_kernel void @v_uaddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 addrspace(1)* %a.ptr, i64 addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i64, i64 addrspace(1)* %a.ptr
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%b.gep = getelementptr inbounds i64, i64 addrspace(1)* %b.ptr
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%a = load i64, i64 addrspace(1)* %a.gep
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%b = load i64, i64 addrspace(1)* %b.gep
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%uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue { i64, i1 } %uadd, 0
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%carry = extractvalue { i64, i1 } %uadd, 1
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store i64 %val, i64 addrspace(1)* %out
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_uaddo_i16:
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; VI: v_add_u16_e32
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; VI: v_cmp_lt_u16_e32
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; GFX9: v_add_u16_e32
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; GFX9: v_cmp_lt_u16_e32
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define amdgpu_kernel void @v_uaddo_i16(i16 addrspace(1)* %out, i1 addrspace(1)* %carryout, i16 addrspace(1)* %a.ptr, i16 addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i16, i16 addrspace(1)* %a.ptr
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%b.gep = getelementptr inbounds i16, i16 addrspace(1)* %b.ptr
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%a = load i16, i16 addrspace(1)* %a.gep
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%b = load i16, i16 addrspace(1)* %b.gep
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%uadd = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 %a, i16 %b)
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%val = extractvalue { i16, i1 } %uadd, 0
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%carry = extractvalue { i16, i1 } %uadd, 1
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store i16 %val, i16 addrspace(1)* %out
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_uaddo_v2i32:
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; SICIVI: v_cmp_lt_i32
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; SICIVI: v_cmp_lt_i32
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; SICIVI: v_add_{{[iu]}}32
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; SICIVI: v_cmp_lt_i32
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; SICIVI: v_cmp_lt_i32
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; SICIVI: v_add_{{[iu]}}32
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define amdgpu_kernel void @v_uaddo_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %carryout, <2 x i32> addrspace(1)* %aptr, <2 x i32> addrspace(1)* %bptr) nounwind {
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%a = load <2 x i32>, <2 x i32> addrspace(1)* %aptr, align 4
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%b = load <2 x i32>, <2 x i32> addrspace(1)* %bptr, align 4
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%sadd = call { <2 x i32>, <2 x i1> } @llvm.uadd.with.overflow.v2i32(<2 x i32> %a, <2 x i32> %b) nounwind
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%val = extractvalue { <2 x i32>, <2 x i1> } %sadd, 0
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%carry = extractvalue { <2 x i32>, <2 x i1> } %sadd, 1
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store <2 x i32> %val, <2 x i32> addrspace(1)* %out, align 4
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%carry.ext = zext <2 x i1> %carry to <2 x i32>
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store <2 x i32> %carry.ext, <2 x i32> addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}s_uaddo_clamp_bit:
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; GCN: v_add_{{i|u|co_u}}32_e32
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; GCN: s_endpgm
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define amdgpu_kernel void @s_uaddo_clamp_bit(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) #0 {
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entry:
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%uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue { i32, i1 } %uadd, 0
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%carry = extractvalue { i32, i1 } %uadd, 1
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%c2 = icmp eq i1 %carry, false
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%cc = icmp eq i32 %a, %b
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br i1 %cc, label %exit, label %if
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if:
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br label %exit
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exit:
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%cout = phi i1 [false, %entry], [%c2, %if]
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i1 %cout, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_uaddo_clamp_bit:
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; GCN: v_add_{{i|u|co_u}}32_e64
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; GCN: s_endpgm
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define amdgpu_kernel void @v_uaddo_clamp_bit(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %a.ptr, i32 addrspace(1)* %b.ptr) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr
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%b.gep = getelementptr inbounds i32, i32 addrspace(1)* %b.ptr
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%a = load i32, i32 addrspace(1)* %a.gep
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%b = load i32, i32 addrspace(1)* %b.gep
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%uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue { i32, i1 } %uadd, 0
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%carry = extractvalue { i32, i1 } %uadd, 1
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%c2 = icmp eq i1 %carry, false
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%cc = icmp eq i32 %a, %b
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br i1 %cc, label %exit, label %if
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if:
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br label %exit
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exit:
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%cout = phi i1 [false, %entry], [%c2, %if]
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i1 %cout, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}sv_uaddo_i128:
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; GCN: v_add
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; GCN: v_addc
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; GCN: v_addc
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; GCN: v_addc
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define amdgpu_cs void @sv_uaddo_i128(i32 addrspace(1)* %out, i128 inreg %a, i128 %b) {
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%uadd = call { i128, i1 } @llvm.uadd.with.overflow.i128(i128 %a, i128 %b)
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%carry = extractvalue { i128, i1 } %uadd, 1
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%carry.ext = zext i1 %carry to i32
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store i32 %carry.ext, i32 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare { i16, i1 } @llvm.uadd.with.overflow.i16(i16, i16) #1
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declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1
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declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64) #1
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declare { i128, i1 } @llvm.uadd.with.overflow.i128(i128, i128) #1
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declare { <2 x i32>, <2 x i1> } @llvm.uadd.with.overflow.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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