fa0b93b5a0
Unfortunately the current call lowering code is built on top of the legacy MVT/DAG based code. However, GlobalISel was not using it the same way. In short, the DAG passes legalized types to the assignment function, and GlobalISel was passing the original raw type if it was simple. I do believe the DAG lowering is conceptually broken since it requires picking a type up front before knowing how/where the value will be passed. This ends up being a problem for AArch64, which wants to pass i1/i8/i16 values as a different size if passed on the stack or in registers. The argument type decision is split across 3 different places which is hard to follow. SelectionDAG builder uses getRegisterTypeForCallingConv to pick a legal type, tablegen gives the illusion of controlling the type, and the target may have additional hacks in the C++ part of the call lowering. AArch64 hacks around this by not using the standard AnalyzeFormalArguments and special casing i1/i8/i16 by looking at the underlying type of the original IR argument. I believe people have generally assumed the calling convention code is processing the original types, and I've discovered a number of dead paths in several targets. x86 actually relies on the opposite behavior from AArch64, and relies on x86_32 and x86_64 sharing calling convention code where the 64-bit cases implicitly do not work on x86_32 due to using the pre-legalized types. AMDGPU targets without legal i16/f16 have always used a broken ABI that promotes to i32/f32. GlobalISel accidentally fixed this to be the ABI we should have, but this fixes it so we're using the worse ABI that is compatible with the DAG. Ideally we would fix the DAG to match the old GlobalISel behavior, but I don't wish to fight that battle. A new native GlobalISel call lowering framework should let the target process the incoming types directly. CCValAssigns select a "ValVT" and "LocVT" but the meanings of these aren't entirely clear. Different targets don't use them consistently, even within their own call lowering code. My current belief is the intent was "ValVT" is supposed to be the legalized value type to use in the end, and and LocVT was supposed to be the ABI passed type (which is also legalized). With the default CCState::Analyze functions always passing the same type for these arguments, these only differ when the TableGen part of the lowering decide to promote the type from one legal type to another. AArch64's i1/i8/i16 hack ends up inverting the meanings of these values, so I had to add an additional hack to let the target interpret how large the argument memory is. Since targets don't consistently interpret ValVT and LocVT, this doesn't produce quite equivalent code to the initial DAG lowerings. I've opted to consistently interpret LocVT as the in-memory size for stack passed values, and ValVT as the register type to assign from that memory. We therefore produce extending loads directly out of the IRTranslator, whereas the DAG would emit regular loads of smaller values. This will also produce loads/stores that are wider than the argument value if the allocated stack slot is larger (and there will be undef padding bytes). If we had the optimizations to reduce load/stores based on truncated values, this wouldn't produce a different end result. Since ValVT/LocVT are more consistently interpreted, we now will emit more G_BITCASTS as requested by the CCAssignFn. For example AArch64 was directly assigning types to some physical vector registers which according to the tablegen spec should have been casted to a vector with a different element type. This also moves the responsibility for inserting G_ASSERT_SEXT/G_ASSERT_ZEXT from the target ValueHandlers into the generic code, which is closer to how SelectionDAGBuilder works. I had to xfail an x86 test since I don't see a quick way to fix it right now (I filed bug 50035 for this). It's broken independently of this change, and only triggers since now we end up with more ands which hit the improperly handled selection pattern. I also observed that FP arguments that need promotion (e.g. f16 passed as f32) are broken, and use regular G_TRUNC and G_ANYEXT. TLDR; the current call lowering infrastructure is bad and nobody has ever understood how it chooses types.
464 lines
9.3 KiB
LLVM
464 lines
9.3 KiB
LLVM
; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v6 -global-isel %s -o - | FileCheck %s
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define void @test_void_return() {
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; CHECK-LABEL: test_void_return:
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; CHECK: bx lr
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entry:
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ret void
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}
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define i32 @test_constant_return_i32() {
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; CHECK-LABEL: test_constant_return_i32:
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; CHECK: mov r0, #42
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; CHECK: bx lr
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entry:
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ret i32 42
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}
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define zeroext i1 @test_zext_i1(i1 %x) {
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; CHECK-LABEL: test_zext_i1
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; CHECK: and r0, r0, #1
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; CHECK: bx lr
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entry:
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ret i1 %x
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}
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define signext i1 @test_sext_i1(i1 %x) {
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; CHECK-LABEL: test_sext_i1
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; CHECK: mov r1, #31
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; CHECK: lsl r0, r0, r1
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; CHECK: asr r0, r0, r1
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; CHECK: bx lr
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entry:
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ret i1 %x
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}
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define zeroext i8 @test_ext_i8(i8 %x) {
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; CHECK-LABEL: test_ext_i8:
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; CHECK: uxtb r0, r0
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; CHECK: bx lr
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entry:
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ret i8 %x
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}
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define signext i16 @test_ext_i16(i16 %x) {
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; CHECK-LABEL: test_ext_i16:
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; CHECK: mov r1, #16
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; CHECK: lsl r0, r0, r1
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; CHECK: asr r0, r0, r1
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; CHECK: bx lr
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entry:
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ret i16 %x
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}
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define void @test_trunc_i32_i16(i32 %v, i16 *%p) {
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; CHECK-LABEL: test_trunc_i32_i16:
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; The trunc doesn't result in any instructions, but we
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; expect the store to be explicitly 16-bit.
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; CHECK: strh r0, [r1]
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; CHECK: bx lr
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entry:
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%v16 = trunc i32 %v to i16
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store i16 %v16, i16 *%p
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ret void
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}
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define void @test_trunc_i32_i8(i32 %v, i8 *%p) {
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; CHECK-LABEL: test_trunc_i32_i8:
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; The trunc doesn't result in any instructions, but we
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; expect the store to be explicitly 8-bit.
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; CHECK: strb r0, [r1]
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; CHECK: bx lr
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entry:
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%v8 = trunc i32 %v to i8
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store i8 %v8, i8 *%p
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ret void
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}
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define i8 @test_add_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: test_add_i8:
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; CHECK: add r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = add i8 %x, %y
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ret i8 %sum
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}
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define i16 @test_add_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: test_add_i16:
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; CHECK: add r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = add i16 %x, %y
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ret i16 %sum
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}
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define i32 @test_add_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: test_add_i32:
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; CHECK: add r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = add i32 %x, %y
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ret i32 %sum
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}
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define i8 @test_sub_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: test_sub_i8:
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; CHECK: sub r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = sub i8 %x, %y
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ret i8 %sum
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}
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define i16 @test_sub_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: test_sub_i16:
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; CHECK: sub r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = sub i16 %x, %y
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ret i16 %sum
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}
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define i32 @test_sub_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: test_sub_i32:
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; CHECK: sub r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = sub i32 %x, %y
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ret i32 %sum
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}
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define i8 @test_mul_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: test_mul_i8:
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; CHECK: mul r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = mul i8 %x, %y
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ret i8 %sum
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}
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define i16 @test_mul_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: test_mul_i16:
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; CHECK: mul r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = mul i16 %x, %y
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ret i16 %sum
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}
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define i32 @test_mul_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: test_mul_i32:
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; CHECK: mul r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = mul i32 %x, %y
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ret i32 %sum
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}
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define i8 @test_and_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: test_and_i8:
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; CHECK: and r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = and i8 %x, %y
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ret i8 %sum
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}
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define i16 @test_and_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: test_and_i16:
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; CHECK: and r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = and i16 %x, %y
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ret i16 %sum
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}
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define i32 @test_and_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: test_and_i32:
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; CHECK: and r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = and i32 %x, %y
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ret i32 %sum
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}
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define i8 @test_or_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: test_or_i8:
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; CHECK: orr r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = or i8 %x, %y
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ret i8 %sum
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}
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define i16 @test_or_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: test_or_i16:
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; CHECK: orr r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = or i16 %x, %y
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ret i16 %sum
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}
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define i32 @test_or_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: test_or_i32:
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; CHECK: orr r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = or i32 %x, %y
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ret i32 %sum
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}
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define i8 @test_xor_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: test_xor_i8:
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; CHECK: eor r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = xor i8 %x, %y
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ret i8 %sum
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}
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define i16 @test_xor_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: test_xor_i16:
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; CHECK: eor r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = xor i16 %x, %y
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ret i16 %sum
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}
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define i32 @test_xor_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: test_xor_i32:
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; CHECK: eor r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = xor i32 %x, %y
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ret i32 %sum
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}
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define i32 @test_stack_args_i32(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) {
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; CHECK-LABEL: test_stack_args_i32:
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; CHECK: add [[P5ADDR:r[0-9]+]], sp, #4
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; CHECK: ldr [[P5:r[0-9]+]], {{.*}}[[P5ADDR]]
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; CHECK: add r0, r2, [[P5]]
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; CHECK: bx lr
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entry:
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%sum = add i32 %p2, %p5
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ret i32 %sum
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}
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define i16 @test_stack_args_mixed(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i8 %p4, i16 %p5) {
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; CHECK-LABEL: test_stack_args_mixed:
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; CHECK: add [[P5ADDR:r[0-9]+]], sp, #4
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; CHECK: ldr [[P5:r[0-9]+]], {{.*}}[[P5ADDR]]
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; CHECK: add r0, r1, [[P5]]
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; CHECK: bx lr
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entry:
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%sum = add i16 %p1, %p5
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ret i16 %sum
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}
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define i16 @test_stack_args_zeroext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i16 zeroext %p4) {
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; CHECK-LABEL: test_stack_args_zeroext:
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; CHECK: mov [[P4ADDR:r[0-9]+]], sp
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; CHECK: ldr [[P4:r[0-9]+]], {{.*}}[[P4ADDR]]
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; CHECK: add r0, r1, [[P4]]
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; CHECK: bx lr
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entry:
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%sum = add i16 %p1, %p4
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ret i16 %sum
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}
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define i8 @test_stack_args_signext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i8 signext %p4) {
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; CHECK-LABEL: test_stack_args_signext:
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; CHECK: mov [[P4ADDR:r[0-9]+]], sp
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; CHECK: ldr [[P4:r[0-9]+]], {{.*}}[[P4ADDR]]
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; CHECK: add r0, r2, [[P4]]
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; CHECK: bx lr
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entry:
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%sum = add i8 %p2, %p4
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ret i8 %sum
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}
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define i8 @test_stack_args_noext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i8 %p4) {
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; CHECK-LABEL: test_stack_args_noext:
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; CHECK: mov [[P4ADDR:r[0-9]+]], sp
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; CHECK: ldr [[P4:r[0-9]+]], {{.*}}[[P4ADDR]]
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; CHECK: add r0, r2, [[P4]]
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; CHECK: bx lr
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entry:
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%sum = add i8 %p2, %p4
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ret i8 %sum
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}
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define i32 @test_ptr_arg_in_reg(i32* %p) {
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; CHECK-LABEL: test_ptr_arg_in_reg:
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; CHECK: ldr r0, [r0]
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; CHECK: bx lr
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entry:
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%v = load i32, i32* %p
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ret i32 %v
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}
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define i32 @test_ptr_arg_on_stack(i32 %f0, i32 %f1, i32 %f2, i32 %f3, i32* %p) {
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; CHECK-LABEL: test_ptr_arg_on_stack:
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; CHECK: mov r0, sp
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; CHECK: ldr r0, [r0]
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; CHECK: ldr r0, [r0]
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; CHECK: bx lr
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entry:
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%v = load i32, i32* %p
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ret i32 %v
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}
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define i8* @test_ptr_ret(i8** %p) {
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; CHECK-LABEL: test_ptr_ret:
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; CHECK: ldr r0, [r0]
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; CHECK: bx lr
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entry:
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%v = load i8*, i8** %p
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ret i8* %v
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}
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define arm_aapcs_vfpcc float @test_float_hard(float %f0, float %f1) {
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; CHECK-LABEL: test_float_hard:
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; CHECK: vadd.f32 s0, s0, s1
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; CHECK: bx lr
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entry:
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%v = fadd float %f0, %f1
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ret float %v
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}
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define arm_aapcscc float @test_float_softfp(float %f0, float %f1) {
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; CHECK-LABEL: test_float_softfp:
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; CHECK-DAG: vmov [[F0:s[0-9]+]], r0
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; CHECK-DAG: vmov [[F1:s[0-9]+]], r1
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; CHECK: vadd.f32 [[FV:s[0-9]+]], [[F0]], [[F1]]
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; CHECK: vmov r0, [[FV]]
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; CHECK: bx lr
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entry:
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%v = fadd float %f0, %f1
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ret float %v
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}
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define arm_aapcs_vfpcc double @test_double_hard(double %f0, double %f1) {
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; CHECK-LABEL: test_double_hard:
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; CHECK: vadd.f64 d0, d0, d1
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; CHECK: bx lr
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entry:
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%v = fadd double %f0, %f1
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ret double %v
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}
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define arm_aapcscc double @test_double_softfp(double %f0, double %f1) {
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; CHECK-LABEL: test_double_softfp:
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; CHECK-DAG: vmov [[F0:d[0-9]+]], r0, r1
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; CHECK-DAG: vmov [[F1:d[0-9]+]], r2, r3
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; CHECK: vadd.f64 [[FV:d[0-9]+]], [[F0]], [[F1]]
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; CHECK: vmov r0, r1, [[FV]]
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; CHECK: bx lr
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entry:
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%v = fadd double %f0, %f1
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ret double %v
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}
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define arm_aapcscc i32 @test_cmp_i32_eq(i32 %a, i32 %b) {
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; CHECK-LABEL: test_cmp_i32_eq:
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; CHECK: mov [[V:r[0-9]+]], #0
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; CHECK: cmp r0, r1
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; CHECK: moveq [[V]], #1
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; CHECK: and r0, [[V]], #1
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; CHECK: bx lr
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entry:
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%v = icmp eq i32 %a, %b
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%r = zext i1 %v to i32
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ret i32 %r
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}
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define arm_aapcscc i32 @test_cmp_ptr_neq(double *%a, double *%b) {
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; CHECK-LABEL: test_cmp_ptr_neq:
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; CHECK: mov [[V:r[0-9]+]], #0
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; CHECK: cmp r0, r1
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; CHECK: movne [[V]], #1
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; CHECK: and r0, [[V]], #1
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; CHECK: bx lr
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entry:
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%v = icmp ne double * %a, %b
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%r = zext i1 %v to i32
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ret i32 %r
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}
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define arm_aapcscc i32 @test_cmp_i16_slt(i16 %a, i16 %b) {
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; CHECK-LABEL: test_cmp_i16_slt:
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; CHECK-DAG: mov [[V:r[0-9]+]], #0
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; CHECK: cmp r0, r1
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; CHECK: movlt [[V]], #1
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; CHECK: and r0, [[V]], #1
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; CHECK: bx lr
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entry:
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%v = icmp slt i16 %a, %b
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%r = zext i1 %v to i32
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ret i32 %r
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}
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define arm_aapcscc i32 @test_select_i32(i32 %a, i32 %b, i1 %cond) {
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; CHECK-LABEL: test_select_i32
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; CHECK: tst r2, #1
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; CHECK: moveq r0, r1
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; CHECK: bx lr
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entry:
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%r = select i1 %cond, i32 %a, i32 %b
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ret i32 %r
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}
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define arm_aapcscc i32* @test_select_ptr(i32* %a, i32* %b, i1 %cond) {
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; CHECK-LABEL: test_select_ptr
|
|
; CHECK: tst r2, #1
|
|
; CHECK: moveq r0, r1
|
|
; CHECK: bx lr
|
|
entry:
|
|
%r = select i1 %cond, i32* %a, i32* %b
|
|
ret i32* %r
|
|
}
|
|
|
|
define arm_aapcscc void @test_br() {
|
|
; CHECK-LABEL: test_br
|
|
; CHECK: [[LABEL:.L[[:alnum:]_]+]]:
|
|
; CHECK: b [[LABEL]]
|
|
entry:
|
|
br label %infinite
|
|
|
|
infinite:
|
|
br label %infinite
|
|
}
|
|
|
|
declare arm_aapcscc void @brcond1()
|
|
declare arm_aapcscc void @brcond2()
|
|
|
|
define arm_aapcscc void @test_brcond(i32 %n) {
|
|
; CHECK-LABEL: test_brcond
|
|
; CHECK: cmp r0
|
|
; CHECK-NEXT: movgt [[RCMP:r[0-9]+]], #1
|
|
; CHECK: tst [[RCMP]], #1
|
|
; CHECK-NEXT: beq [[FALSE:.L[[:alnum:]_]+]]
|
|
; CHECK: bl brcond1
|
|
; CHECK: [[FALSE]]:
|
|
; CHECK: bl brcond2
|
|
entry:
|
|
%cmp = icmp sgt i32 %n, 0
|
|
br i1 %cmp, label %if.true, label %if.false
|
|
|
|
if.true:
|
|
call arm_aapcscc void @brcond1()
|
|
br label %if.end
|
|
|
|
if.false:
|
|
call arm_aapcscc void @brcond2()
|
|
br label %if.end
|
|
|
|
if.end:
|
|
ret void
|
|
}
|