b1d47467e2
This commit removes the artificial types <512 x i1> and <1024 x i1>
from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal on
Hexagon.
It may cause existing bitcode files to become invalid.
* Converting between vector predicates and vector registers must be
done explicitly via vandvrt/vandqrt instructions (their intrinsics),
i.e. (for 64-byte mode):
%Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1)
%V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1)
The conversion intrinsics are:
declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32)
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32)
They are all pure.
* Vector predicate values cannot be loaded/stored directly. This directly
reflects the architecture restriction. Loading and storing or vector
predicates must be done indirectly via vector registers and explicit
conversions via vandvrt/vandqrt instructions.
34 lines
1.3 KiB
LLVM
34 lines
1.3 KiB
LLVM
; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
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; CHECK: q{{[0-3]}} = vand(v{{[0-9]+}},r{{[0-9]+}})
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; CHECK: q{{[0-3]}} = vand(v{{[0-9]+}},r{{[0-9]+}})
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; CHECK: q{{[0-3]}} = and(q{{[0-3]}},q{{[0-3]}})
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target triple = "hexagon"
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@g0 = common global <16 x i32> zeroinitializer, align 64
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; Function Attrs: nounwind
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define i32 @f0() #0 {
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b0:
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%v0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)
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%v1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v0, i32 -1)
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%v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2)
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%v3 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v2, i32 -1)
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%v4 = tail call <64 x i1> @llvm.hexagon.V6.pred.and(<64 x i1> %v1, <64 x i1> %v3)
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%v5 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v4, i32 -1)
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store <16 x i32> %v5, <16 x i32>* @g0, align 64, !tbaa !0
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ret i32 0
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}
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declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
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declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
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declare <64 x i1> @llvm.hexagon.V6.pred.and(<64 x i1>, <64 x i1>) #1
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declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"omnipotent char", !2, i64 0}
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!2 = !{!"Simple C/C++ TBAA"}
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