657bb7262d
Previously ADD & ADDA (as well as SUB & SUBA) instructions are mixed together, which not only violated Motorola assembly's syntax but also made asm parsing more difficult. This patch separates these two kinds of instructions migrate rest of the tests from test/CodeGen/M68k/Encoding/Arithmetic to test/MC/M68k/Arithmetic. Note that we observed minor regressions on codegen quality: Sometimes isel uses ADD instead of ADDA even the latter can lead to shorter sequence of code. This issue implies that some isel patterns might need to be updated.
103 lines
2.9 KiB
LLVM
103 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
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;; TODO All these can be improved
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define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
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; CHECK-LABEL: t1:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: move.w (6,%sp), %d0
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; CHECK-NEXT: and.l #65535, %d0
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; CHECK-NEXT: sub.l #26, %d0
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; CHECK-NEXT: shi %d0
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; CHECK-NEXT: and.l #255, %d0
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; CHECK-NEXT: lsl.l #5, %d0
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; CHECK-NEXT: rts
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entry:
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%0 = icmp ugt i16 %x, 26 ; <i1> [#uses=1]
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%iftmp.1.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1]
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ret i16 %iftmp.1.0
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}
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define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp {
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; CHECK-LABEL: t2:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: move.w (6,%sp), %d0
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; CHECK-NEXT: and.l #65535, %d0
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; CHECK-NEXT: sub.l #26, %d0
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; CHECK-NEXT: scs %d0
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; CHECK-NEXT: and.l #255, %d0
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; CHECK-NEXT: lsl.l #5, %d0
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; CHECK-NEXT: rts
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entry:
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%0 = icmp ult i16 %x, 26 ; <i1> [#uses=1]
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%iftmp.0.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1]
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ret i16 %iftmp.0.0
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}
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define fastcc i64 @t3(i64 %x) nounwind readnone ssp {
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; CHECK-LABEL: t3:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: suba.l #4, %sp
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; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
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; CHECK-NEXT: move.l #0, %d2
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; CHECK-NEXT: sub.l #18, %d1
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; CHECK-NEXT: subx.l %d2, %d0
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; CHECK-NEXT: scs %d0
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; CHECK-NEXT: move.l %d0, %d1
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; CHECK-NEXT: and.l #255, %d1
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; CHECK-NEXT: and.l #1, %d1
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; CHECK-NEXT: lsl.l #6, %d1
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; CHECK-NEXT: move.l %d2, %d0
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; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
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; CHECK-NEXT: adda.l #4, %sp
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; CHECK-NEXT: rts
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entry:
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%0 = icmp ult i64 %x, 18 ; <i1> [#uses=1]
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%iftmp.2.0 = select i1 %0, i64 64, i64 0 ; <i64> [#uses=1]
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ret i64 %iftmp.2.0
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}
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define i8 @t5(i32 %a) {
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; CHECK-LABEL: t5:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0: ; %entry
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; CHECK-NEXT: move.l #31, %d1
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: lsr.l %d1, %d0
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; CHECK-NEXT: eori.b #1, %d0
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; CHECK-NEXT: ; kill: def $bd0 killed $bd0 killed $d0
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; CHECK-NEXT: rts
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entry:
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%.lobit = lshr i32 %a, 31
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%trunc = trunc i32 %.lobit to i8
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%.not = xor i8 %trunc, 1
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ret i8 %.not
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}
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;
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; TODO: Should it be like this?
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; cmp.l
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; smi
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; since we are intereseted in sign bit only
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; and.l in the end is superfluous
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define zeroext i1 @t6(i32 %a) {
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; CHECK-LABEL: t6:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0: ; %entry
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; CHECK-NEXT: move.l #31, %d0
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; CHECK-NEXT: move.l (4,%sp), %d1
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; CHECK-NEXT: lsr.l %d0, %d1
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; CHECK-NEXT: eori.b #1, %d1
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; CHECK-NEXT: move.l %d1, %d0
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; CHECK-NEXT: and.l #255, %d0
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; CHECK-NEXT: rts
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entry:
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%.lobit = lshr i32 %a, 31
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%trunc = trunc i32 %.lobit to i1
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%.not = xor i1 %trunc, 1
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ret i1 %.not
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}
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