657bb7262d
Previously ADD & ADDA (as well as SUB & SUBA) instructions are mixed together, which not only violated Motorola assembly's syntax but also made asm parsing more difficult. This patch separates these two kinds of instructions migrate rest of the tests from test/CodeGen/M68k/Encoding/Arithmetic to test/MC/M68k/Arithmetic. Note that we observed minor regressions on codegen quality: Sometimes isel uses ADD instead of ADDA even the latter can lead to shorter sequence of code. This issue implies that some isel patterns might need to be updated.
115 lines
3.6 KiB
YAML
115 lines
3.6 KiB
YAML
# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj \
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# RUN: -code-model=small -relocation-model=pic -o - \
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# RUN: | extract-section .text -h \
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# RUN: | FileCheck %s
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#------------------------------------------------------------------------------
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# Test branch relaxation. By default codegen choses smallest branch instruction,
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# during object code generation it might get clear that offset does not fit and
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# bigger instruction is required.
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#------------------------------------------------------------------------------
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--- # TIGHT
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# The offset for the small branch is from the PC value, which points to the
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# next instruction, because there is no extension word here.
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# 000 CHECK: 6078
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# 002 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 00C CHECK-SAME: 23f9 0000 0000 0000 0000
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# 016 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 020 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 02A CHECK-SAME: 23f9 0000 0000 0000 0000
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# 034 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 03E CHECK-SAME: 23f9 0000 0000 0000 0000
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# 048 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 052 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 05C CHECK-SAME: 23f9 0000 0000 0000 0000
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# 066 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 070 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 07A CHECK-SAME: d0bc 0000 0000
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# 080 CHECK-SAME: 4e75
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name: TIGHT
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body: |
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bb.0:
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successors: %bb.2
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BRA8 %bb.2
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bb.1:
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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bb.2:
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$d0 = ADD32di $d0, 0, implicit-def $ccr
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RET 0, $d0
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...
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--- # RELAXED
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# 084 CHECK-SAME 6000 0084
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# 088 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 092 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 09C CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0A6 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0B0 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0BA CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0C4 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0CE CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0D8 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0E2 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0EC CHECK-SAME: 23f9 0000 0000 0000 0000
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# 0F6 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 100 CHECK-SAME: 23f9 0000 0000 0000 0000
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# 10A CHECK-SAME: d0bc 0000 0000
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# 110 CHECK-SAME: 4e75
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name: RELAXED
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body: |
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bb.0:
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successors: %bb.2
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BRA8 %bb.2
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bb.1:
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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MOV32bb 0, 0, implicit-def $ccr
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bb.2:
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$d0 = ADD32di $d0, 0, implicit-def $ccr
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RET 0, $d0
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...
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--- # ZERO
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# Because of the way M68k encodes branches it is not possible to encode 0
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# offset with the smallest insruction(0 in the offset field means exension word
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# is used) thus we switch to the wider instruction.
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# 114 CHECK-SAME: 6000 0002
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# 118 CHECK-SAME: d0bc 0000 0000
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# 11E CHECK-SAME: 4e75
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name: ZERO
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body: |
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bb.0:
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successors: %bb.1
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BRA8 %bb.1
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bb.1:
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$d0 = ADD32di $d0, 0, implicit-def $ccr
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RET 0, $d0
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...
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