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clang-p2996/llvm/test/CodeGen/NVPTX
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Steffen Larsen 1b4c85fc02 [NVPTX] Add NVPTX intrinsics for CUDA PTX 6.5 ldmatrix instructions 
Adds NVPTX intrinsics for the CUDA PTX `ldmatrix.sync.aligned` instructions added in PTX 6.5.

PTX ISA description of `ldmatrix.sync.aligned`: https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#warp-level-matrix-instructions-ldmatrix

Authored-by: Steffen Larsen <steffen.larsen@codeplay.com>

Reviewed By: tra

Differential Revision: https://reviews.llvm.org/D107046
2021-08-06 16:13:35 -07:00
..
access-non-generic.ll
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add-128bit.ll
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addrspacecast-gvar.ll
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addrspacecast.ll
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aggr-param.ll
[NVPTX] Fix emitting aggregate parameters
2014-01-28 18:35:29 +00:00
aggregate-return.ll
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alias.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
annotations.ll
Whitespace cleanup in test/CodeGen/NVPTX/annotations.ll.
2016-12-14 22:32:55 +00:00
arg-lowering.ll
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arithmetic-fp-sm20.ll
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arithmetic-int.ll
[NVPTX] expand mul_lohi to mul_lo and mul_hi
2016-01-22 19:47:26 +00:00
async-copy.ll
[Clang][NVPTX] Add NVPTX intrinsics and builtins for CUDA PTX cp.async instructions
2021-05-17 09:46:59 -07:00
atomic-lower-local.ll
[NVPTX] Enable lowering of atomics on local memory
2021-04-26 20:12:12 -04:00
atomics-sm60.ll
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atomics-with-scope.ll
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atomics.ll
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barrier.ll
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bfe.ll
[NVPTX] Add isel patterns for bit-field extract (bfe)
2014-06-27 18:35:27 +00:00
branch-fold.ll
…
bug17709.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
bug21465.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
bug22246.ll
[NVPTX] Generate a more optimal sequence for select of i1
2015-01-26 19:52:20 +00:00
bug22322.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
bug26185-2.ll
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bug26185.ll
[NVPTX] Handle ldg created from sign-/zero-extended load
2016-04-05 12:38:01 +00:00
bug41651.ll
[NVPTX] Fix PR41651
2019-07-30 19:52:01 +00:00
bypass-div.ll
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call-with-alloca-buffer.ll
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callchain.ll
…
calling-conv.ll
IR: Make metadata typeless in assembly
2014-12-15 19:07:53 +00:00
calls-with-phi.ll
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combine-min-max.ll
…
compare-int.ll
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constant-vectors.ll
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convergent-mir-call.ll
…
convert-fp.ll
[NVPTX] Add fptosi tests to convert-fp.ll.
2017-01-15 16:55:54 +00:00
convert-int-sm20.ll
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ctlz.ll
NFC - Various typo fixes in tests
2018-07-04 13:28:39 +00:00
ctpop.ll
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cttz.ll
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disable-opt.ll
[NVPTX] Disable performance optimizations when OptLevel==None
2016-02-04 04:15:36 +00:00
div-ri.ll
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divrem-combine.ll
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envreg.ll
[NVPTX] Add support for envreg reads
2014-06-27 18:35:21 +00:00
extloadv.ll
[NVPTX] expand extload/truncstore for vectors of floats
2015-07-01 21:32:42 +00:00
f16-instructions.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
f16x2-instructions.ll
Fix the default alignment of i1 vectors.
2021-07-31 14:09:59 -07:00
fast-math.ll
[NVPTX] Add select(cc,binop(),binop()) fast-math tests
2021-07-18 15:30:24 +01:00
fcos-no-fast-math.ll
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fma-assoc.ll
…
fma-disable.ll
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fma.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
fns.ll
[NVPTX,CUDA] Added llvm.nvvm.fns intrinsic and matching __nvvm_fns builtin in clang.
2017-12-06 17:50:05 +00:00
fp16.ll
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
2015-02-27 21:17:42 +00:00
fp-contract.ll
[NVPTX] Improve handling of FP fusion
2014-07-17 18:10:09 +00:00
fp-literals.ll
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fsin-no-fast-math.ll
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function-align.ll
[NVPTXAsmPrinter] do not print .align on function headers
2015-03-12 01:50:30 +00:00
generic-to-nvvm-ir.ll
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generic-to-nvvm.ll
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global-addrspace.ll
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global-ctor-empty.ll
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global-ctor.ll
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global-dtor.ll
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global-ordering.ll
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global-variable-big.ll
[NVPTX] Support global variables of integer type larger than i64.
2017-01-18 00:29:53 +00:00
global-visibility.ll
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globals_init.ll
The constant initialization for globals in NVPTX is generated as an
2015-06-09 16:29:34 +00:00
globals_lowering.ll
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gvar-init.ll
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half.ll
[NVPTX] add support for initializing fp16 arrays.
2018-04-06 22:25:08 +00:00
i1-global.ll
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i1-int-to-fp.ll
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i1-param.ll
IR: Make metadata typeless in assembly
2014-12-15 19:07:53 +00:00
i8-param.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
i128-global.ll
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i128-param.ll
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i128-retval.ll
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i128-struct.ll
[NVPTX] Add lowering of i128 numbers as struct fields
2018-12-01 00:21:52 +00:00
idioms.ll
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imad.ll
…
inline-asm.ll
[NVPTX] Add 'b' asm constraint
2014-06-27 18:36:06 +00:00
inlineasm-output-template.ll
[AsmPrinter] refactor to support %c w/ GlobalAddress'
2019-04-26 18:45:04 +00:00
intrin-nocapture.ll
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intrinsic-old.ll
[NewPM][NVPTX] Port NVPTX opt passes
2021-01-07 15:12:35 -08:00
intrinsics.ll
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isspacep.ll
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ld-addrspace.ll
[NVPTX] Added a feature to use short pointers for const/local/shared AS.
2018-05-09 23:46:19 +00:00
ld-generic.ll
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
2015-02-27 21:17:42 +00:00
ld-st-addrrspace.py
tests/CodeGen: Use %python lit substitution when invoking python
2021-07-06 18:46:36 -07:00
ldg-invariant.ll
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ldparam-v4.ll
[NVPTX] Unify vectorization of load/stores of aggregate arguments and return values.
2017-02-21 22:56:05 +00:00
ldu-i8.ll
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ldu-ldg.ll
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ldu-reg-plus-offset.ll
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libcall-fulfilled.ll
[NVPTX] CUDA does provide malloc/free since compute capability 2.X
2021-03-15 22:45:56 -05:00
libcall-instruction.ll
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libcall-intrinsic.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
lit.local.cfg
[Clang][NVPTX] Add NVPTX intrinsics and builtins for CUDA PTX 6.5 and 7.0 WMMA and MMA instructions
2021-06-29 15:44:07 -07:00
load-sext-i1.ll
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load-store.ll
SelectionDAG: accommodate atomic floating stores.
2019-05-10 11:23:04 +00:00
load-with-non-coherent-cache.ll
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LoadStoreVectorizer.ll
[NVPTX] Added support for .f16x2 instructions.
2017-02-23 22:38:24 +00:00
local-stack-frame.ll
[NVPTX] Move NVPTXPeephole after NVPTXPrologEpilogPass
2015-07-01 20:08:06 +00:00
loop-vectorize.ll
[NVPTX] declare no vector registers
2015-07-10 04:31:56 +00:00
lower-aggr-copies.ll
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lower-alloca.ll
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lower-args.ll
[NVPTX] Avoid temp copy of byval kernel parameters.
2021-03-15 14:27:22 -07:00
lower-byval-args.ll
[NVPTX] Handle bitcast and ASC(101) when trying to avoid argument copy.
2021-04-06 13:06:00 -07:00
lower-kernel-ptr-arg.ll
[NVPTX] Avoid temp copy of byval kernel parameters.
2021-03-15 14:27:22 -07:00
machine-sink.ll
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MachineSink-call.ll
[NVPTX] Annotate call machine instructions as calls.
2016-02-17 17:46:50 +00:00
MachineSink-convergent.ll
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managed.ll
IR: Make metadata typeless in assembly
2014-12-15 19:07:53 +00:00
match.ll
[NVPTX] added match.{any,all}.sync instructions, intrinsics & builtins.
2017-09-26 17:07:23 +00:00
math-intrins.ll
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mbarrier.ll
[Clang][NVPTX] Add NVPTX intrinsics and builtins for CUDA PTX cp.async instructions
2021-05-17 09:46:59 -07:00
minmax-negative.ll
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misaligned-vector-ldst.ll
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module-inline-asm.ll
[NVPTX] Fix for NVPTX module asm regression
2020-06-24 11:17:09 -07:00
mulwide.ll
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named-barriers.ll
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noduplicate-syncthreads.ll
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nofunc.ll
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nounroll.ll
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nvcl-param-align.ll
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nvvm-reflect-arch.ll
[NVPTX][NewPM] Re-enable NVVMReflectPass
2021-02-08 13:58:17 -08:00
nvvm-reflect-module-flag.ll
[NewPM][NVPTX] Port NVPTX opt passes
2021-01-07 15:12:35 -08:00
nvvm-reflect.ll
[NewPM][NVPTX] Port NVPTX opt passes
2021-01-07 15:12:35 -08:00
param-align.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
param-load-store.ll
Fix the default alignment of i1 vectors.
2021-07-31 14:09:59 -07:00
pow2_mask_cmp.ll
[TargetLowering] Add i1 condition for bit comparison fold
2020-10-27 12:22:20 +00:00
pr13291-i1-store.ll
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pr16278.ll
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pr17529.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
proxy-reg-erasure-mir.ll
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proxy-reg-erasure-ptx.ll
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read-global-variable-constant.ll
[NVPTX] Lower loads from global constants using ld.global.nc (aka LDG).
2018-02-28 23:58:05 +00:00
redux-sync.ll
[Clang][NVPTX] Add NVPTX intrinsics and builtins for CUDA PTX redux.sync instructions
2021-05-17 09:46:59 -07:00
refl1.ll
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reg-copy.ll
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reg-types.ll
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rotate.ll
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sched1.ll
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sched2.ll
…
sext-in-reg.ll
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sext-params.ll
[NVPTX] Handle signext/zeroext attributes properly
2013-07-01 12:58:58 +00:00
shfl-p.ll
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shfl-sync-p.ll
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shfl-sync.ll
[NVPTX] Implemented shfl.sync instruction and supporting intrinsics/builtins.
2017-09-20 21:23:07 +00:00
shfl.ll
…
shift-parts.ll
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simple-call.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
sm-version-20.ll
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sm-version-21.ll
…
sm-version-30.ll
…
sm-version-32.ll
…
sm-version-35.ll
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sm-version-37.ll
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sm-version-50.ll
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sm-version-52.ll
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sm-version-53.ll
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sm-version-60.ll
…
sm-version-61.ll
…
sm-version-62.ll
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sm-version-70.ll
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speculative-execution-divergent-target.ll
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sqrt-approx.ll
[DAGCombine] Remove the check for unsafe-fp-math when we are checking the AFN
2021-01-11 02:25:53 +00:00
st-addrspace.ll
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st-generic.ll
[NVPTX] Rename registers %fl -> %fd and %rl -> %rd
2014-07-16 16:26:58 +00:00
surf-read-cuda.ll
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surf-read.ll
…
surf-write-cuda.ll
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surf-write.ll
IR: Make metadata typeless in assembly
2014-12-15 19:07:53 +00:00
symbol-naming.ll
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TailDuplication-convergent.ll
…
tex-read-cuda.ll
…
tex-read.ll
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texsurf-queries.ll
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tid-range.ll
…
tuple-literal.ll
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vec8.ll
Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB."
2017-05-18 18:50:05 +00:00
vec-param-load.ll
[NVPTX] Unify vectorization of load/stores of aggregate arguments and return values.
2017-02-21 22:56:05 +00:00
vector-args.ll
[NVPTX] Add support for vectorized function return values
2013-06-28 17:57:55 +00:00
vector-call.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
vector-compare.ll
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
2015-02-27 21:17:42 +00:00
vector-global.ll
[NVPTX] Fix bugs related to isSingleValueType
2014-12-17 17:59:04 +00:00
vector-loads.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
vector-select.ll
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
2015-02-27 21:17:42 +00:00
vector-stores.ll
Add a target legalize hook for SplitVectorOperand (again)
2013-07-26 13:28:29 +00:00
vectorize-misaligned.ll
[NVPTX] Implement isLegalToVectorizeLoadChain
2018-08-27 17:29:43 +00:00
vote.ll
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weak-global.ll
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
2015-02-27 21:17:42 +00:00
weak-linkage.ll
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wmma.py
[NVPTX] Add NVPTX intrinsics for CUDA PTX 6.5 ldmatrix instructions
2021-08-06 16:13:35 -07:00
zeroext-32bit.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00