841077a7e9
Summary: The bit order of the has_vec and longtbtable bits in the traceback table generated by the XL compiler flipped at some point after v12.1. This is different from the definition is the AIX header debug.h. The change in the XL compiler that caused the deviation from the OS header definition was unintentional. Since both orderings are extant and the XL compiler runtime also expects the ordering defined by the OS, we will correct the output from LLVM to match the defined ordering given by the OS (which is also consistent with the Assembler Language Reference). Mitigation for traceback tables encoded with the wrong ordering is required for either ordering. Reviewers: XingXue, HubertTong Differential Revision: https://reviews.llvm.org/D105487
178 lines
7.2 KiB
LLVM
178 lines
7.2 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
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; RUN: -mattr=-altivec -simplifycfg-require-and-preserve-domtree=1 < %s | \
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; RUN: FileCheck --check-prefixes=ASM,ASM32 %s
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; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
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; RUN: -mattr=-altivec -simplifycfg-require-and-preserve-domtree=1 < %s | \
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; RUN: FileCheck --check-prefixes=ASM,ASM64 %s
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@_ZTIi = external constant i8*
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define void @_Z9throwFuncv() {
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entry:
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%exception = call i8* @__cxa_allocate_exception(i32 4) #2
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%0 = bitcast i8* %exception to i32*
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store i32 1, i32* %0, align 16
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call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null) #3
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unreachable
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}
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; ASM: ._Z9throwFuncv:
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; ASM: bl .__cxa_allocate_exception[PR]
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; ASM: nop
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; ASM32: lwz 4, L..C0(2)
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; ASM64: ld 4, L..C0(2)
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; ASM: bl .__cxa_throw[PR]
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; ASM: nop
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define i32 @_Z9catchFuncv() personality i8* bitcast (i32 (...)* @__xlcxx_personality_v1 to i8*) {
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entry:
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%retval = alloca i32, align 4
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%exn.slot = alloca i8*, align 4
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%ehselector.slot = alloca i32, align 4
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%0 = alloca i32, align 4
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invoke void @_Z9throwFuncv()
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to label %invoke.cont unwind label %lpad
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invoke.cont: ; preds = %entry
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br label %try.cont
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lpad: ; preds = %entry
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%1 = landingpad { i8*, i32 }
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catch i8* bitcast (i8** @_ZTIi to i8*)
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%2 = extractvalue { i8*, i32 } %1, 0
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store i8* %2, i8** %exn.slot, align 4
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%3 = extractvalue { i8*, i32 } %1, 1
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store i32 %3, i32* %ehselector.slot, align 4
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br label %catch.dispatch
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catch.dispatch: ; preds = %lpad
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%sel = load i32, i32* %ehselector.slot, align 4
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%4 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) #2
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%matches = icmp eq i32 %sel, %4
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br i1 %matches, label %catch, label %eh.resume
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catch: ; preds = %catch.dispatch
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%exn = load i8*, i8** %exn.slot, align 4
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%5 = call i8* @__cxa_begin_catch(i8* %exn) #2
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%6 = bitcast i8* %5 to i32*
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%7 = load i32, i32* %6, align 4
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store i32 %7, i32* %0, align 4
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store i32 2, i32* %retval, align 4
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call void @__cxa_end_catch() #2
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br label %return
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try.cont: ; preds = %invoke.cont
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store i32 1, i32* %retval, align 4
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br label %return
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return: ; preds = %try.cont, %catch
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%8 = load i32, i32* %retval, align 4
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ret i32 %8
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eh.resume: ; preds = %catch.dispatch
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%exn1 = load i8*, i8** %exn.slot, align 4
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%sel2 = load i32, i32* %ehselector.slot, align 4
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%lpad.val = insertvalue { i8*, i32 } undef, i8* %exn1, 0
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%lpad.val3 = insertvalue { i8*, i32 } %lpad.val, i32 %sel2, 1
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resume { i8*, i32 } %lpad.val3
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}
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; ASM: ._Z9catchFuncv:
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; ASM: L..func_begin0:
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; ASM: # %bb.0: # %entry
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; ASM: mflr 0
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; ASM: L..tmp0:
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; ASM: bl ._Z9throwFuncv
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; ASM: nop
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; ASM: L..tmp1:
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; ASM: # %bb.1: # %invoke.cont
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; ASM: li 3, 1
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; ASM: L..BB1_2: # %return
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; ASM: mtlr 0
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; ASM: blr
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; ASM: L..BB1_3: # %lpad
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; ASM: L..tmp2:
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; ASM: bl .__cxa_begin_catch[PR]
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; ASM: nop
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; ASM: bl .__cxa_end_catch[PR]
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; ASM: nop
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; ASM: b L..BB1_2
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; ASM: L.._Z9catchFuncv0:
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; ASM: .vbyte 4, 0x00000000 # Traceback table begin
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; ASM: .byte 0x00 # Version = 0
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; ASM: .byte 0x09 # Language = CPlusPlus
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; ASM: .byte 0x20 # -IsGlobaLinkage, -IsOutOfLineEpilogOrPrologue
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; ASM: # +HasTraceBackTableOffset, -IsInternalProcedure
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; ASM: # -HasControlledStorage, -IsTOCless
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; ASM: # -IsFloatingPointPresent
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; ASM: # -IsFloatingPointOperationLogOrAbortEnabled
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; ASM: .byte 0x41 # -IsInterruptHandler, +IsFunctionNamePresent, -IsAllocaUsed
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; ASM: # OnConditionDirective = 0, -IsCRSaved, +IsLRSaved
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; ASM: .byte 0x80 # +IsBackChainStored, -IsFixup, NumOfFPRsSaved = 0
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; ASM: .byte 0x80 # +HasExtensionTable, -HasVectorInfo, NumOfGPRsSaved = 0
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; ASM: .byte 0x00 # NumberOfFixedParms = 0
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; ASM: .byte 0x01 # NumberOfFPParms = 0, +HasParmsOnStack
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; ASM: .vbyte 4, L.._Z9catchFuncv0-._Z9catchFuncv # Function size
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; ASM: .vbyte 2, 0x000d # Function name len = 13
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; ASM: .byte "_Z9catchFuncv" # Function Name
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; ASM: .byte 0x08 # ExtensionTableFlag = TB_EH_INFO
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; ASM: .align 2
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; ASM32: .vbyte 4, L..C1-TOC[TC0] # EHInfo Table
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; ASM64: .vbyte 8, L..C1-TOC[TC0] # EHInfo Table
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; ASM: L..func_end0:
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; ASM: .csect .gcc_except_table[RO],2
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; ASM: .align 2
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; ASM: GCC_except_table1:
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; ASM: L..exception0:
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; ASM: .byte 255 # @LPStart Encoding = omit
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; ASM32: .byte 187 # @TType Encoding = indirect datarel sdata4
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; ASM64: .byte 188 # @TType Encoding = indirect datarel sdata8
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; ASM32: .byte 37
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; ASM64: .byte 41
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; ASM: .byte 3 # Call site Encoding = udata4
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; ASM: .byte 26
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; ASM: .vbyte 4, L..tmp0-L..func_begin0 # >> Call Site 1 <<
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; ASM: .vbyte 4, L..tmp1-L..tmp0 # Call between L..tmp0 and L..tmp1
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; ASM: .vbyte 4, L..tmp2-L..func_begin0 # jumps to L..tmp2
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; ASM: .byte 1 # On action: 1
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; ASM: .vbyte 4, L..tmp1-L..func_begin0 # >> Call Site 2 <<
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; ASM: .vbyte 4, L..func_end0-L..tmp1 # Call between L..tmp1 and L..func_end0
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; ASM: .vbyte 4, 0 # has no landing pad
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; ASM: .byte 0 # On action: cleanup
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; ASM: L..cst_end0:
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; ASM: .byte 1 # >> Action Record 1 <<
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; ASM: # Catch TypeInfo 1
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; ASM: .byte 0 # No further actions
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; ASM: .align 2
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; ASM: # >> Catch TypeInfos <<
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; ASM32: .vbyte 4, L..C0-TOC[TC0] # TypeInfo 1
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; ASM64: .vbyte 8, L..C0-TOC[TC0] # TypeInfo 1
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; ASM: L..ttbase0:
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; ASM: .align 2
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; ASM: .csect .eh_info_table[RW],2
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; ASM: __ehinfo.1:
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; ASM: .vbyte 4, 0
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; ASM32: .align 2
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; ASM32: .vbyte 4, GCC_except_table1
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; ASM32: .vbyte 4, __xlcxx_personality_v1[DS]
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; ASM64: .align 3
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; ASM64: .vbyte 8, GCC_except_table1
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; ASM64: .vbyte 8, __xlcxx_personality_v1[DS]
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; ASM: .toc
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; ASM: L..C0:
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; ASM: .tc _ZTIi[TC],_ZTIi[UA]
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; ASM: L..C1:
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; ASM: .tc __ehinfo.1[TC],__ehinfo.1
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declare i8* @__cxa_allocate_exception(i32)
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declare void @__cxa_throw(i8*, i8*, i8*)
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declare i32 @__xlcxx_personality_v1(...)
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declare i32 @llvm.eh.typeid.for(i8*)
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declare i8* @__cxa_begin_catch(i8*)
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declare void @__cxa_end_catch()
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