03e7fefff8
Extend shuffle canonicalization and conversion of shuffles fed by vectorized scalars to big endian subtargets. For big endian subtargets, loads and direct moves of scalars into vector registers put the data in the correct element for SCALAR_TO_VECTOR if the data type is 8 bytes wide. However, if the data type is narrower, the value still ends up in the wrong place - althouth a different wrong place than on little endian targets. This patch extends the combine that keeps values where they are if they feed a shuffle to big endian targets. Differential revision: https://reviews.llvm.org/D100478
26 lines
1.1 KiB
LLVM
26 lines
1.1 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck --check-prefix=CHECK-LE \
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; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck \
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; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s
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define <16 x i8> @test(i32* %s, i32* %t) {
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; CHECK-LE-LABEL: test:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: lfiwzx f0, 0, r3
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; CHECK-LE-NEXT: xxspltw v2, vs0, 1
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; CHECK-LE-NEXT: blr
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lfiwzx f0, 0, r3
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; CHECK-NEXT: xxspltw v2, vs0, 1
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; CHECK-NEXT: blr
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entry:
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%0 = bitcast i32* %s to <4 x i8>*
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%1 = load <4 x i8>, <4 x i8>* %0, align 4
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%2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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ret <16 x i8> %2
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}
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