a08fc1361a
On PowerPC, VSRpRC represents the pairs of even and odd VSX register, and VRRC corresponds to higher 32 VSX registers. In some cases, extra copies are produced when handling incoming VRRC arguments with VSRpRC. This patch changes allocation order of VSRpRC to eliminate this kind of copy. Stack frame sizes may increase if allocating non-volatile registers, and some other vector copies happen. They need fix in future changes. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D104855
115 lines
5.1 KiB
LLVM
115 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -disable-lsr \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr10 < %s | FileCheck %s
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -disable-lsr \
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; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr10 < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-BE
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; This test checks the PPCLoopInstrFormPrep pass supports the lxvp and stxvp
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; intrinsics so we generate more dq-form instructions instead of x-forms.
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%_elem_type_of_x = type <{ double }>
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%_elem_type_of_y = type <{ double }>
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define void @foo(i64* %.n, [0 x %_elem_type_of_x]* %.x, [0 x %_elem_type_of_y]* %.y, <2 x double>* %.sum) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld r5, 0(r3)
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; CHECK-NEXT: cmpdi r5, 1
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; CHECK-NEXT: bltlr cr0
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; CHECK-NEXT: # %bb.1: # %_loop_1_do_.lr.ph
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; CHECK-NEXT: addi r3, r4, 1
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; CHECK-NEXT: addi r4, r5, -1
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; CHECK-NEXT: lxv vs0, 0(r6)
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; CHECK-NEXT: rldicl r4, r4, 60, 4
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; CHECK-NEXT: addi r4, r4, 1
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; CHECK-NEXT: mtctr r4
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; CHECK-NEXT: .p2align 5
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; CHECK-NEXT: .LBB0_2: # %_loop_1_do_
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; CHECK-NEXT: #
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; CHECK-NEXT: lxvp vsp34, 0(r3)
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; CHECK-NEXT: lxvp vsp36, 32(r3)
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; CHECK-NEXT: addi r3, r3, 128
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; CHECK-NEXT: xvadddp vs0, vs0, vs35
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; CHECK-NEXT: xvadddp vs0, vs0, vs34
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; CHECK-NEXT: xvadddp vs0, vs0, vs37
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; CHECK-NEXT: xvadddp vs0, vs0, vs36
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; CHECK-NEXT: bdnz .LBB0_2
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; CHECK-NEXT: # %bb.3: # %_loop_1_loopHeader_._return_bb_crit_edge
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; CHECK-NEXT: stxv vs0, 0(r6)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: foo:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: ld r5, 0(r3)
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; CHECK-BE-NEXT: cmpdi r5, 1
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; CHECK-BE-NEXT: bltlr cr0
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; CHECK-BE-NEXT: # %bb.1: # %_loop_1_do_.lr.ph
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; CHECK-BE-NEXT: addi r3, r4, 1
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; CHECK-BE-NEXT: addi r4, r5, -1
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; CHECK-BE-NEXT: lxv vs0, 0(r6)
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; CHECK-BE-NEXT: rldicl r4, r4, 60, 4
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; CHECK-BE-NEXT: addi r4, r4, 1
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; CHECK-BE-NEXT: mtctr r4
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; CHECK-BE-NEXT: .p2align 5
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; CHECK-BE-NEXT: .LBB0_2: # %_loop_1_do_
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; CHECK-BE-NEXT: #
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; CHECK-BE-NEXT: lxvp vsp34, 0(r3)
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; CHECK-BE-NEXT: lxvp vsp36, 32(r3)
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; CHECK-BE-NEXT: addi r3, r3, 128
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; CHECK-BE-NEXT: xvadddp vs0, vs0, vs34
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; CHECK-BE-NEXT: xvadddp vs0, vs0, vs35
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; CHECK-BE-NEXT: xvadddp vs0, vs0, vs36
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; CHECK-BE-NEXT: xvadddp vs0, vs0, vs37
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; CHECK-BE-NEXT: bdnz .LBB0_2
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; CHECK-BE-NEXT: # %bb.3: # %_loop_1_loopHeader_._return_bb_crit_edge
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; CHECK-BE-NEXT: stxv vs0, 0(r6)
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; CHECK-BE-NEXT: blr
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entry:
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%_val_n_2 = load i64, i64* %.n, align 8
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%_grt_tmp7 = icmp slt i64 %_val_n_2, 1
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br i1 %_grt_tmp7, label %_return_bb, label %_loop_1_do_.lr.ph
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_loop_1_do_.lr.ph: ; preds = %entry
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%x_rvo_based_addr_5 = getelementptr inbounds [0 x %_elem_type_of_x], [0 x %_elem_type_of_x]* %.x, i64 0, i64 -1
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%.sum.promoted = load <2 x double>, <2 x double>* %.sum, align 16
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br label %_loop_1_do_
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_loop_1_do_: ; preds = %_loop_1_do_.lr.ph, %_loop_1_do_
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%_val_sum_9 = phi <2 x double> [ %.sum.promoted, %_loop_1_do_.lr.ph ], [ %_add_tmp49, %_loop_1_do_ ]
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%i.08 = phi i64 [ 1, %_loop_1_do_.lr.ph ], [ %_loop_1_update_loop_ix, %_loop_1_do_ ]
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%x_ix_dim_0_6 = getelementptr %_elem_type_of_x, %_elem_type_of_x* %x_rvo_based_addr_5, i64 %i.08
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%x_ix_dim_0_ = bitcast %_elem_type_of_x* %x_ix_dim_0_6 to i8*
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%0 = getelementptr i8, i8* %x_ix_dim_0_, i64 1
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%1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %0)
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%2 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> %1)
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%.fca.0.extract1 = extractvalue { <16 x i8>, <16 x i8> } %2, 0
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%.fca.1.extract2 = extractvalue { <16 x i8>, <16 x i8> } %2, 1
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%3 = getelementptr i8, i8* %x_ix_dim_0_, i64 33
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%4 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %3)
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%5 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> %4)
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%.fca.0.extract = extractvalue { <16 x i8>, <16 x i8> } %5, 0
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%.fca.1.extract = extractvalue { <16 x i8>, <16 x i8> } %5, 1
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%6 = bitcast <16 x i8> %.fca.0.extract1 to <2 x double>
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%_add_tmp23 = fadd contract <2 x double> %_val_sum_9, %6
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%7 = bitcast <16 x i8> %.fca.1.extract2 to <2 x double>
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%_add_tmp32 = fadd contract <2 x double> %_add_tmp23, %7
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%8 = bitcast <16 x i8> %.fca.0.extract to <2 x double>
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%_add_tmp40 = fadd contract <2 x double> %_add_tmp32, %8
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%9 = bitcast <16 x i8> %.fca.1.extract to <2 x double>
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%_add_tmp49 = fadd contract <2 x double> %_add_tmp40, %9
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%_loop_1_update_loop_ix = add nuw nsw i64 %i.08, 16
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%_grt_tmp = icmp sgt i64 %_loop_1_update_loop_ix, %_val_n_2
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br i1 %_grt_tmp, label %_loop_1_loopHeader_._return_bb_crit_edge, label %_loop_1_do_
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_loop_1_loopHeader_._return_bb_crit_edge: ; preds = %_loop_1_do_
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store <2 x double> %_add_tmp49, <2 x double>* %.sum, align 16
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br label %_return_bb
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_return_bb: ; preds = %_loop_1_loopHeader_._return_bb_crit_edge, %entry
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ret void
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}
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declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*)
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declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)
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