a08fc1361a
On PowerPC, VSRpRC represents the pairs of even and odd VSX register, and VRRC corresponds to higher 32 VSX registers. In some cases, extra copies are produced when handling incoming VRRC arguments with VSRpRC. This patch changes allocation order of VSRpRC to eliminate this kind of copy. Stack frame sizes may increase if allocating non-volatile registers, and some other vector copies happen. They need fix in future changes. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D104855
227 lines
8.3 KiB
LLVM
227 lines
8.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s --check-prefix=LE-PAIRED
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=BE-PAIRED
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@f = common dso_local local_unnamed_addr global <512 x i1> zeroinitializer, align 16
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@g = common dso_local local_unnamed_addr global <256 x i1> zeroinitializer, align 16
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define dso_local void @testLdSt(i64 %SrcIdx, i64 %DstIdx) {
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; LE-PAIRED-LABEL: testLdSt:
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; LE-PAIRED: # %bb.0: # %entry
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; LE-PAIRED-NEXT: plxv vs1, f@PCREL+96(0), 1
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; LE-PAIRED-NEXT: plxv vs0, f@PCREL+112(0), 1
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; LE-PAIRED-NEXT: plxv vs3, f@PCREL+64(0), 1
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; LE-PAIRED-NEXT: plxv vs2, f@PCREL+80(0), 1
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; LE-PAIRED-NEXT: pstxv vs0, f@PCREL+176(0), 1
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; LE-PAIRED-NEXT: pstxv vs1, f@PCREL+160(0), 1
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; LE-PAIRED-NEXT: pstxv vs2, f@PCREL+144(0), 1
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; LE-PAIRED-NEXT: pstxv vs3, f@PCREL+128(0), 1
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; LE-PAIRED-NEXT: blr
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;
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; BE-PAIRED-LABEL: testLdSt:
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; BE-PAIRED: # %bb.0: # %entry
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; BE-PAIRED-NEXT: addis r3, r2, f@toc@ha
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; BE-PAIRED-NEXT: addi r3, r3, f@toc@l
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; BE-PAIRED-NEXT: lxv vs1, 80(r3)
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; BE-PAIRED-NEXT: lxv vs0, 64(r3)
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; BE-PAIRED-NEXT: lxv vs3, 112(r3)
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; BE-PAIRED-NEXT: lxv vs2, 96(r3)
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; BE-PAIRED-NEXT: stxv vs1, 144(r3)
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; BE-PAIRED-NEXT: stxv vs0, 128(r3)
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; BE-PAIRED-NEXT: stxv vs3, 176(r3)
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; BE-PAIRED-NEXT: stxv vs2, 160(r3)
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; BE-PAIRED-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 1
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%0 = load <512 x i1>, <512 x i1>* %arrayidx, align 64
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%arrayidx1 = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 2
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store <512 x i1> %0, <512 x i1>* %arrayidx1, align 64
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ret void
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}
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define dso_local void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
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; LE-PAIRED-LABEL: testXLdSt:
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; LE-PAIRED: # %bb.0: # %entry
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; LE-PAIRED-NEXT: sldi r3, r3, 6
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; LE-PAIRED-NEXT: paddi r5, 0, f@PCREL, 1
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; LE-PAIRED-NEXT: add r6, r5, r3
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; LE-PAIRED-NEXT: lxv vs1, 32(r6)
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; LE-PAIRED-NEXT: lxv vs0, 48(r6)
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; LE-PAIRED-NEXT: lxvx vs3, r5, r3
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; LE-PAIRED-NEXT: lxv vs2, 16(r6)
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; LE-PAIRED-NEXT: sldi r3, r4, 6
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; LE-PAIRED-NEXT: stxvx vs3, r5, r3
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; LE-PAIRED-NEXT: add r3, r5, r3
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; LE-PAIRED-NEXT: stxv vs0, 48(r3)
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; LE-PAIRED-NEXT: stxv vs1, 32(r3)
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; LE-PAIRED-NEXT: stxv vs2, 16(r3)
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; LE-PAIRED-NEXT: blr
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;
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; BE-PAIRED-LABEL: testXLdSt:
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; BE-PAIRED: # %bb.0: # %entry
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; BE-PAIRED-NEXT: addis r5, r2, f@toc@ha
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; BE-PAIRED-NEXT: sldi r3, r3, 6
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; BE-PAIRED-NEXT: addi r5, r5, f@toc@l
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; BE-PAIRED-NEXT: add r6, r5, r3
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; BE-PAIRED-NEXT: lxvx vs0, r5, r3
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; BE-PAIRED-NEXT: sldi r3, r4, 6
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; BE-PAIRED-NEXT: lxv vs1, 16(r6)
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; BE-PAIRED-NEXT: lxv vs3, 48(r6)
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; BE-PAIRED-NEXT: lxv vs2, 32(r6)
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; BE-PAIRED-NEXT: stxvx vs0, r5, r3
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; BE-PAIRED-NEXT: add r3, r5, r3
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; BE-PAIRED-NEXT: stxv vs1, 16(r3)
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; BE-PAIRED-NEXT: stxv vs3, 48(r3)
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; BE-PAIRED-NEXT: stxv vs2, 32(r3)
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; BE-PAIRED-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 %SrcIdx
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%0 = load <512 x i1>, <512 x i1>* %arrayidx, align 64
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%arrayidx1 = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 %DstIdx
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store <512 x i1> %0, <512 x i1>* %arrayidx1, align 64
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ret void
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}
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define dso_local void @testUnalignedLdSt() {
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; LE-PAIRED-LABEL: testUnalignedLdSt:
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; LE-PAIRED: # %bb.0: # %entry
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; LE-PAIRED-NEXT: plxv vs1, f@PCREL+43(0), 1
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; LE-PAIRED-NEXT: plxv vs0, f@PCREL+59(0), 1
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; LE-PAIRED-NEXT: plxv vs3, f@PCREL+11(0), 1
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; LE-PAIRED-NEXT: plxv vs2, f@PCREL+27(0), 1
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; LE-PAIRED-NEXT: pstxv vs0, f@PCREL+67(0), 1
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; LE-PAIRED-NEXT: pstxv vs1, f@PCREL+51(0), 1
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; LE-PAIRED-NEXT: pstxv vs2, f@PCREL+35(0), 1
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; LE-PAIRED-NEXT: pstxv vs3, f@PCREL+19(0), 1
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; LE-PAIRED-NEXT: blr
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;
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; BE-PAIRED-LABEL: testUnalignedLdSt:
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; BE-PAIRED: # %bb.0: # %entry
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; BE-PAIRED-NEXT: addis r3, r2, f@toc@ha
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; BE-PAIRED-NEXT: li r4, 11
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; BE-PAIRED-NEXT: addi r3, r3, f@toc@l
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; BE-PAIRED-NEXT: lxvx vs0, r3, r4
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; BE-PAIRED-NEXT: li r4, 27
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; BE-PAIRED-NEXT: lxvx vs1, r3, r4
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; BE-PAIRED-NEXT: li r4, 43
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; BE-PAIRED-NEXT: lxvx vs2, r3, r4
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; BE-PAIRED-NEXT: li r4, 59
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; BE-PAIRED-NEXT: lxvx vs3, r3, r4
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; BE-PAIRED-NEXT: li r4, 35
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; BE-PAIRED-NEXT: stxvx vs1, r3, r4
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; BE-PAIRED-NEXT: li r4, 19
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; BE-PAIRED-NEXT: stxvx vs0, r3, r4
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; BE-PAIRED-NEXT: li r4, 67
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; BE-PAIRED-NEXT: stxvx vs3, r3, r4
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; BE-PAIRED-NEXT: li r4, 51
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; BE-PAIRED-NEXT: stxvx vs2, r3, r4
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; BE-PAIRED-NEXT: blr
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entry:
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%0 = bitcast <512 x i1>* @f to i8*
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%add.ptr = getelementptr inbounds i8, i8* %0, i64 11
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%add.ptr1 = getelementptr inbounds i8, i8* %0, i64 19
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%1 = bitcast i8* %add.ptr to <512 x i1>*
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%2 = bitcast i8* %add.ptr1 to <512 x i1>*
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%3 = load <512 x i1>, <512 x i1>* %1, align 64
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store <512 x i1> %3, <512 x i1>* %2, align 64
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ret void
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}
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define dso_local void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) {
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; LE-PAIRED-LABEL: testLdStPair:
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; LE-PAIRED: # %bb.0: # %entry
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; LE-PAIRED-NEXT: plxv v3, g@PCREL+32(0), 1
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; LE-PAIRED-NEXT: plxv v2, g@PCREL+48(0), 1
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; LE-PAIRED-NEXT: pstxv v3, g@PCREL+64(0), 1
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; LE-PAIRED-NEXT: pstxv v2, g@PCREL+80(0), 1
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; LE-PAIRED-NEXT: blr
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;
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; BE-PAIRED-LABEL: testLdStPair:
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; BE-PAIRED: # %bb.0: # %entry
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; BE-PAIRED-NEXT: addis r3, r2, g@toc@ha
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; BE-PAIRED-NEXT: addi r3, r3, g@toc@l
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; BE-PAIRED-NEXT: lxv v3, 48(r3)
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; BE-PAIRED-NEXT: lxv v2, 32(r3)
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; BE-PAIRED-NEXT: stxv v3, 80(r3)
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; BE-PAIRED-NEXT: stxv v2, 64(r3)
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; BE-PAIRED-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 1
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%0 = load <256 x i1>, <256 x i1>* %arrayidx, align 64
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%arrayidx1 = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 2
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store <256 x i1> %0, <256 x i1>* %arrayidx1, align 64
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ret void
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}
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define dso_local void @testXLdStPair(i64 %SrcIdx, i64 %DstIdx) {
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; LE-PAIRED-LABEL: testXLdStPair:
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; LE-PAIRED: # %bb.0: # %entry
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; LE-PAIRED-NEXT: sldi r3, r3, 5
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; LE-PAIRED-NEXT: paddi r5, 0, g@PCREL, 1
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; LE-PAIRED-NEXT: add r6, r5, r3
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; LE-PAIRED-NEXT: lxvx v3, r5, r3
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; LE-PAIRED-NEXT: sldi r3, r4, 5
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; LE-PAIRED-NEXT: lxv v2, 16(r6)
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; LE-PAIRED-NEXT: add r4, r5, r3
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; LE-PAIRED-NEXT: stxvx v3, r5, r3
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; LE-PAIRED-NEXT: stxv v2, 16(r4)
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; LE-PAIRED-NEXT: blr
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;
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; BE-PAIRED-LABEL: testXLdStPair:
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; BE-PAIRED: # %bb.0: # %entry
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; BE-PAIRED-NEXT: addis r5, r2, g@toc@ha
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; BE-PAIRED-NEXT: sldi r3, r3, 5
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; BE-PAIRED-NEXT: addi r5, r5, g@toc@l
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; BE-PAIRED-NEXT: add r6, r5, r3
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; BE-PAIRED-NEXT: lxvx v2, r5, r3
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; BE-PAIRED-NEXT: sldi r3, r4, 5
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; BE-PAIRED-NEXT: lxv v3, 16(r6)
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; BE-PAIRED-NEXT: add r4, r5, r3
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; BE-PAIRED-NEXT: stxvx v2, r5, r3
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; BE-PAIRED-NEXT: stxv v3, 16(r4)
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; BE-PAIRED-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 %SrcIdx
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%0 = load <256 x i1>, <256 x i1>* %arrayidx, align 64
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%arrayidx1 = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 %DstIdx
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store <256 x i1> %0, <256 x i1>* %arrayidx1, align 64
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ret void
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}
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define dso_local void @testUnalignedLdStPair() {
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; LE-PAIRED-LABEL: testUnalignedLdStPair:
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; LE-PAIRED: # %bb.0: # %entry
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; LE-PAIRED-NEXT: plxv v3, g@PCREL+11(0), 1
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; LE-PAIRED-NEXT: plxv v2, g@PCREL+27(0), 1
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; LE-PAIRED-NEXT: pstxv v3, g@PCREL+19(0), 1
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; LE-PAIRED-NEXT: pstxv v2, g@PCREL+35(0), 1
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; LE-PAIRED-NEXT: blr
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;
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; BE-PAIRED-LABEL: testUnalignedLdStPair:
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; BE-PAIRED: # %bb.0: # %entry
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; BE-PAIRED-NEXT: addis r3, r2, g@toc@ha
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; BE-PAIRED-NEXT: li r4, 11
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; BE-PAIRED-NEXT: addi r3, r3, g@toc@l
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; BE-PAIRED-NEXT: lxvx v2, r3, r4
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; BE-PAIRED-NEXT: li r4, 27
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; BE-PAIRED-NEXT: lxvx v3, r3, r4
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; BE-PAIRED-NEXT: li r4, 35
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; BE-PAIRED-NEXT: stxvx v3, r3, r4
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; BE-PAIRED-NEXT: li r4, 19
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; BE-PAIRED-NEXT: stxvx v2, r3, r4
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; BE-PAIRED-NEXT: blr
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entry:
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%0 = bitcast <256 x i1>* @g to i8*
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%add.ptr = getelementptr inbounds i8, i8* %0, i64 11
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%add.ptr1 = getelementptr inbounds i8, i8* %0, i64 19
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%1 = bitcast i8* %add.ptr to <256 x i1>*
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%2 = bitcast i8* %add.ptr1 to <256 x i1>*
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%3 = load <256 x i1>, <256 x i1>* %1, align 64
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store <256 x i1> %3, <256 x i1>* %2, align 64
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ret void
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}
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