caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
ef2cdfe393d01cd4935c806387ac912b5a2c8ced
clang-p2996/llvm/test/CodeGen/PowerPC/mma-outer-product.ll
Stefan Pintilie 1a6dc92be7 [PowerPC] Inefficient register allocation of ACC registers results in many copies. 
ACC registers are a combination of four consecutive vector registers.
If the vector registers are assigned first this often forces a number
of copies to appear just before the ACC register is created. If the ACC
register is assigned first then fewer copies are generated when the vector
registers are assigned.

This patch tries to force the register allocator to assign the ACC registers first
and then the UACC registers and then the vector pair registers. It does this
by changing the priority of the register classes.

This patch also adds hints to help the register allocator assign UACC registers from
known ACC registers and vector pair registers from known UACC registers.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D105854
2021-07-20 10:53:40 -05:00

1821 lines
61 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-track-subreg-liveness -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-track-subreg-liveness -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4, i8* %ptr) {
; CHECK-LABEL: intrinsics1:
; CHECK: # %bb.0:
; CHECK-NEXT: vmr v1, v4
; CHECK-NEXT: vmr v4, v3
; CHECK-NEXT: ld r3, 96(r1)
; CHECK-NEXT: vmr v0, v2
; CHECK-NEXT: xxlor vs3, v5, v5
; CHECK-NEXT: xxlor vs0, v0, v0
; CHECK-NEXT: xxlor vs1, v1, v1
; CHECK-NEXT: xxlor vs2, v4, v4
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvi4ger8pp acc0, v2, v3
; CHECK-NEXT: xvf16ger2pp acc0, v2, v1
; CHECK-NEXT: pmxvf32gerpn acc0, v3, v5, 0, 0
; CHECK-NEXT: vmr v3, v2
; CHECK-NEXT: vmr v2, v5
; CHECK-NEXT: pmxvf64gernp acc0, vsp34, v0, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r3)
; CHECK-NEXT: stxv vs1, 32(r3)
; CHECK-NEXT: stxv vs2, 16(r3)
; CHECK-NEXT: stxv vs3, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: intrinsics1:
; CHECK-BE: # %bb.0:
; CHECK-BE-NEXT: vmr v1, v4
; CHECK-BE-NEXT: vmr v4, v3
; CHECK-BE-NEXT: ld r3, 112(r1)
; CHECK-BE-NEXT: vmr v0, v2
; CHECK-BE-NEXT: xxlor vs3, v5, v5
; CHECK-BE-NEXT: xxlor vs0, v0, v0
; CHECK-BE-NEXT: xxlor vs1, v1, v1
; CHECK-BE-NEXT: xxlor vs2, v4, v4
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: xvi4ger8pp acc0, v2, v3
; CHECK-BE-NEXT: xvf16ger2pp acc0, v2, v1
; CHECK-BE-NEXT: pmxvf32gerpn acc0, v3, v5, 0, 0
; CHECK-BE-NEXT: vmr v3, v2
; CHECK-BE-NEXT: vmr v2, v5
; CHECK-BE-NEXT: pmxvf64gernp acc0, vsp34, v0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: blr
%1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc3, <16 x i8> %vc2, <16 x i8> %vc4)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc2)
%3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
%4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> %3, <16 x i8> %vc2, <16 x i8> %vc4, i32 0, i32 0)
%5 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc4, <16 x i8> %vc1)
%6 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> %4, <256 x i1> %5, <16 x i8> %vc1, i32 0, i32 0)
%7 = bitcast i8* %ptr to <512 x i1>*
store <512 x i1> %6, <512 x i1>* %7, align 64
ret void
}
declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
define void @intrinsics2(<16 x i8>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3, <16 x i8>* %ptr4, i8* %ptr) {
; CHECK-LABEL: intrinsics2:
; CHECK: # %bb.0:
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: lxv v4, 0(r5)
; CHECK-NEXT: lxv v5, 0(r6)
; CHECK-NEXT: xxlor vs0, v2, v2
; CHECK-NEXT: xxlor vs1, v3, v3
; CHECK-NEXT: xxlor vs2, v4, v4
; CHECK-NEXT: xxlor vs3, v5, v5
; CHECK-NEXT: vmr v1, v2
; CHECK-NEXT: vmr v0, v5
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvi8ger4pp acc0, v2, v3
; CHECK-NEXT: xvf16ger2pn acc0, v2, v4
; CHECK-NEXT: pmxvf32gernn acc0, v3, v5, 0, 0
; CHECK-NEXT: pmxvf64gernn acc0, vsp32, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs3, 0(r3)
; CHECK-NEXT: stxv vs2, 0(r4)
; CHECK-NEXT: stxv vs1, 0(r5)
; CHECK-NEXT: stxv vs0, 0(r6)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: intrinsics2:
; CHECK-BE: # %bb.0:
; CHECK-BE-NEXT: lxv v2, 0(r3)
; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: lxv v4, 0(r5)
; CHECK-BE-NEXT: lxv v5, 0(r6)
; CHECK-BE-NEXT: xxlor vs0, v2, v2
; CHECK-BE-NEXT: xxlor vs1, v3, v3
; CHECK-BE-NEXT: xxlor vs2, v4, v4
; CHECK-BE-NEXT: xxlor vs3, v5, v5
; CHECK-BE-NEXT: vmr v1, v2
; CHECK-BE-NEXT: vmr v0, v5
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: xvi8ger4pp acc0, v2, v3
; CHECK-BE-NEXT: xvf16ger2pn acc0, v2, v4
; CHECK-BE-NEXT: pmxvf32gernn acc0, v3, v5, 0, 0
; CHECK-BE-NEXT: pmxvf64gernn acc0, vsp32, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs1, 0(r4)
; CHECK-BE-NEXT: stxv vs2, 0(r5)
; CHECK-BE-NEXT: stxv vs3, 0(r6)
; CHECK-BE-NEXT: blr
%vc1 = load <16 x i8>, <16 x i8>* %ptr1, align 16
%vc2 = load <16 x i8>, <16 x i8>* %ptr2, align 16
%vc3 = load <16 x i8>, <16 x i8>* %ptr3, align 16
%vc4 = load <16 x i8>, <16 x i8>* %ptr4, align 16
%1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc2)
%3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
%4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1> %3, <16 x i8> %vc2, <16 x i8> %vc4, i32 0, i32 0)
%5 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc4, <16 x i8> %vc1)
%6 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %4, <256 x i1> %5, <16 x i8> %vc1, i32 0, i32 0)
%7 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %6)
%8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 0
%9 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 1
%10 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 2
%11 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 3
%12 = bitcast i8* %ptr to <512 x i1>*
store <16 x i8> %8, <16 x i8>* %ptr1, align 16
store <16 x i8> %9, <16 x i8>* %ptr2, align 16
store <16 x i8> %10, <16 x i8>* %ptr3, align 16
store <16 x i8> %11, <16 x i8>* %ptr4, align 16
ret void
}
define void @test1(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvi4ger8 acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test1:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xvi4ger8 acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> %vc, <16 x i8> %vc)
%1 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8>, <16 x i8>)
define void @test2(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvi4ger8pp acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test2:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: xvi4ger8pp acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test3(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pmxvi4ger8 acc0, v2, v2, 0, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test3:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: pmxvi4ger8 acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi4ger8(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%1 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvi4ger8(<16 x i8>, <16 x i8>, i32, i32, i32)
define void @test4(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvi4ger8pp acc0, v2, v2, 0, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test4:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: pmxvi4ger8pp acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvi4ger8pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvi4ger8pp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)
define void @test5(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvi8ger4 acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test5:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xvi8ger4 acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4(<16 x i8> %vc, <16 x i8> %vc)
%1 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvi8ger4(<16 x i8>, <16 x i8>)
define void @test6(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test6:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvi8ger4pp acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test6:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: xvi8ger4pp acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test7(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test7:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pmxvi8ger4 acc0, v2, v2, 0, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test7:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: pmxvi8ger4 acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%1 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvi8ger4(<16 x i8>, <16 x i8>, i32, i32, i32)
define void @test8(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvi8ger4pp acc0, v2, v2, 0, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test8:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: pmxvi8ger4pp acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvi8ger4pp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)
define void @test9(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test9:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvi16ger2s acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test9:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xvi16ger2s acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2s(<16 x i8> %vc, <16 x i8> %vc)
%1 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvi16ger2s(<16 x i8>, <16 x i8>)
define void @test10(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test10:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvi16ger2spp acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test10:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: xvi16ger2spp acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2spp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvi16ger2spp(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test11(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test11:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pmxvi16ger2s acc0, v2, v2, 0, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test11:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: pmxvi16ger2s acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2s(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%1 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2s(<16 x i8>, <16 x i8>, i32, i32, i32)
define void @test12(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test12:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvi16ger2spp acc0, v2, v2, 0, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test12:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: pmxvi16ger2spp acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2spp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2spp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)
define void @test13(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test13:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvf16ger2 acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test13:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xvf16ger2 acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2(<16 x i8> %vc, <16 x i8> %vc)
%1 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvf16ger2(<16 x i8>, <16 x i8>)
define void @test14(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test14:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf16ger2pp acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test14:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: xvf16ger2pp acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test15(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test15:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf16ger2pn acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test15:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: xvf16ger2pn acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test16(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf16ger2np acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test16:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: xvf16ger2np acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2np(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvf16ger2np(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test17(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test17:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf16ger2nn acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test17:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: xvf16ger2nn acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2nn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvf16ger2nn(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test18(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test18:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pmxvf16ger2 acc0, v2, v2, 0, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test18:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: pmxvf16ger2 acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%1 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2(<16 x i8>, <16 x i8>, i32, i32, i32)
define void @test19(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test19:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvf16ger2pp acc0, v2, v2, 0, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test19:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: pmxvf16ger2pp acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)
define void @test20(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test20:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvf16ger2pn acc0, v2, v2, 0, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test20:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: pmxvf16ger2pn acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2pn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)
define void @test21(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test21:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvf16ger2np acc0, v2, v2, 0, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test21:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: pmxvf16ger2np acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2np(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2np(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)
define void @test22(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test22:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvf16ger2nn acc0, v2, v2, 0, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test22:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: pmxvf16ger2nn acc0, v2, v2, 0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2nn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2nn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)
define void @test23(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test23:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvf32ger acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test23:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xvf32ger acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xvf32ger(<16 x i8> %vc, <16 x i8> %vc)
%1 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvf32ger(<16 x i8>, <16 x i8>)
define void @test24(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test24:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf32gerpp acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test24:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: xvf32gerpp acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test25(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test25:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf32gerpn acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test25:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: xvf32gerpn acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test26(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test26:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf32gernp acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test26:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: xvf32gernp acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test27(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test27:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf32gernn acc0, v2, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test27:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: xvf32gernn acc0, v2, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf32gernn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvf32gernn(<512 x i1>, <16 x i8>, <16 x i8>)
define void @test28(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test28:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pmxvf32ger acc0, v2, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test28:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: pmxvf32ger acc0, v2, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32ger(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0)
%1 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %0, <512 x i1>* %1, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvf32ger(<16 x i8>, <16 x i8>, i32, i32)
define void @test29(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test29:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvf32gerpp acc0, v2, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test29:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: pmxvf32gerpp acc0, v2, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvf32gerpp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32)
define void @test30(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test30:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvf32gerpn acc0, v2, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test30:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: pmxvf32gerpn acc0, v2, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32)
define void @test31(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test31:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvf32gernp acc0, v2, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test31:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: pmxvf32gernp acc0, v2, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32)
define void @test32(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: pmxvf32gernn acc0, v2, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test32:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: pmxvf32gernn acc0, v2, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32)
define void @test33(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test33:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: lxv v4, 16(r4)
; CHECK-NEXT: xvf64ger acc0, vsp36, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test33:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v5, 16(r4)
; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: xvf64ger acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vpp to <256 x i1>*
%1 = load <256 x i1>, <256 x i1>* %0, align 32
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> %1, <16 x i8> %vc)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1>, <16 x i8>)
define void @test34(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test34:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: lxv v4, 16(r4)
; CHECK-NEXT: xvf64gerpp acc0, vsp36, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test34:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: lxv v5, 16(r4)
; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: xvf64gerpp acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = bitcast i8* %vpp to <256 x i1>*
%3 = load <256 x i1>, <256 x i1>* %2, align 32
%4 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>)
define void @test35(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test35:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: lxv v4, 16(r4)
; CHECK-NEXT: xvf64gerpn acc0, vsp36, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test35:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: lxv v5, 16(r4)
; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: xvf64gerpn acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = bitcast i8* %vpp to <256 x i1>*
%3 = load <256 x i1>, <256 x i1>* %2, align 32
%4 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpn(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvf64gerpn(<512 x i1>, <256 x i1>, <16 x i8>)
define void @test36(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test36:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: lxv v4, 16(r4)
; CHECK-NEXT: xvf64gernp acc0, vsp36, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test36:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: lxv v5, 16(r4)
; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: xvf64gernp acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = bitcast i8* %vpp to <256 x i1>*
%3 = load <256 x i1>, <256 x i1>* %2, align 32
%4 = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>)
define void @test37(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test37:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: lxv v4, 16(r4)
; CHECK-NEXT: xvf64gernn acc0, vsp36, v2
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test37:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: lxv v5, 16(r4)
; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: xvf64gernn acc0, vsp36, v2
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = bitcast i8* %vpp to <256 x i1>*
%3 = load <256 x i1>, <256 x i1>* %2, align 32
%4 = tail call <512 x i1> @llvm.ppc.mma.xvf64gernn(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.xvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>)
define void @test38(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test38:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: lxv v4, 16(r4)
; CHECK-NEXT: pmxvf64ger acc0, vsp36, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test38:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v5, 16(r4)
; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: pmxvf64ger acc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vpp to <256 x i1>*
%1 = load <256 x i1>, <256 x i1>* %0, align 32
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1> %1, <16 x i8> %vc, i32 0, i32 0)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1>, <16 x i8>, i32, i32)
define void @test39(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test39:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: lxv v4, 16(r4)
; CHECK-NEXT: pmxvf64gerpp acc0, vsp36, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test39:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: lxv v5, 16(r4)
; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: pmxvf64gerpp acc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = bitcast i8* %vpp to <256 x i1>*
%3 = load <256 x i1>, <256 x i1>* %2, align 32
%4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gerpp(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc, i32 0, i32 0)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)
define void @test40(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test40:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: lxv v4, 16(r4)
; CHECK-NEXT: pmxvf64gerpn acc0, vsp36, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test40:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: lxv v5, 16(r4)
; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: pmxvf64gerpn acc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = bitcast i8* %vpp to <256 x i1>*
%3 = load <256 x i1>, <256 x i1>* %2, align 32
%4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gerpn(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc, i32 0, i32 0)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvf64gerpn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)
define void @test41(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test41:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: lxv v4, 16(r4)
; CHECK-NEXT: pmxvf64gernp acc0, vsp36, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test41:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: lxv v5, 16(r4)
; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: pmxvf64gernp acc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = bitcast i8* %vpp to <256 x i1>*
%3 = load <256 x i1>, <256 x i1>* %2, align 32
%4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc, i32 0, i32 0)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)
define void @test42(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
; CHECK-LABEL: test42:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
; CHECK-NEXT: lxv vs0, 48(r3)
; CHECK-NEXT: lxv vs3, 0(r3)
; CHECK-NEXT: lxv vs2, 16(r3)
; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: lxv v5, 0(r4)
; CHECK-NEXT: lxv v4, 16(r4)
; CHECK-NEXT: pmxvf64gernn acc0, vsp36, v2, 0, 0
; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r7)
; CHECK-NEXT: stxv vs1, 32(r7)
; CHECK-NEXT: stxv vs2, 16(r7)
; CHECK-NEXT: stxv vs3, 0(r7)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test42:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: lxv v5, 16(r4)
; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: pmxvf64gernn acc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r7)
; CHECK-BE-NEXT: stxv vs0, 0(r7)
; CHECK-BE-NEXT: stxv vs3, 48(r7)
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = bitcast i8* %vpp to <256 x i1>*
%3 = load <256 x i1>, <256 x i1>* %2, align 32
%4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc, i32 0, i32 0)
%5 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %4, <512 x i1>* %5, align 64
ret void
}
declare <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)
Reference in New Issue View Git Blame Copy Permalink