1a6dc92be7
ACC registers are a combination of four consecutive vector registers. If the vector registers are assigned first this often forces a number of copies to appear just before the ACC register is created. If the ACC register is assigned first then fewer copies are generated when the vector registers are assigned. This patch tries to force the register allocator to assign the ACC registers first and then the UACC registers and then the vector pair registers. It does this by changing the priority of the register classes. This patch also adds hints to help the register allocator assign UACC registers from known ACC registers and vector pair registers from known UACC registers. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D105854
334 lines
17 KiB
LLVM
334 lines
17 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
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; RUN: | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -ppc-track-subreg-liveness < %s | FileCheck %s --check-prefix=TRACKLIVE
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%0 = type <{ double }>
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%1 = type <{ double }>
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define void @acc_regalloc(i32* %arg, [0 x %0]* %arg1, [0 x %1]* %arg2) local_unnamed_addr {
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; CHECK-LABEL: acc_regalloc:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: lwz r3, 0(r3)
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; CHECK-NEXT: lxv v4, 0(0)
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; CHECK-NEXT: xxlxor v0, v0, v0
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; CHECK-NEXT: xxlxor v1, v1, v1
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; CHECK-NEXT: stfd f14, -144(r1) # 8-byte Folded Spill
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; CHECK-NEXT: stfd f15, -136(r1) # 8-byte Folded Spill
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; CHECK-NEXT: xxlxor v2, v2, v2
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; CHECK-NEXT: li r6, 1
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; CHECK-NEXT: li r4, 16
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; CHECK-NEXT: extswsli r3, r3, 3
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; CHECK-NEXT: xvmaddadp v1, v4, v1
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; CHECK-NEXT: lxvdsx v5, 0, r3
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; CHECK-NEXT: xvmaddadp v0, v5, v0
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_1: # %bb9
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; CHECK-NEXT: #
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; CHECK-NEXT: addi r6, r6, 2
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; CHECK-NEXT: lxv vs1, -64(r5)
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; CHECK-NEXT: lxv vs2, -16(r5)
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; CHECK-NEXT: lxv vs0, 16(0)
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; CHECK-NEXT: vmr v9, v0
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; CHECK-NEXT: xxlxor v10, v10, v10
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; CHECK-NEXT: xxlxor v7, v7, v7
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; CHECK-NEXT: mulld r6, r6, r3
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; CHECK-NEXT: xvmaddadp v9, vs1, v2
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; CHECK-NEXT: xxlxor v8, v8, v8
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; CHECK-NEXT: xvmaddadp v10, vs2, v10
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; CHECK-NEXT: xvmaddadp v7, vs0, v5
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; CHECK-NEXT: xvmuldp v6, vs0, v2
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; CHECK-NEXT: xvmaddadp v7, v2, v2
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; CHECK-NEXT: xvmaddadp v6, v2, v2
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; CHECK-NEXT: lxvdsx v14, r6, r4
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; CHECK-NEXT: xvmaddadp v8, vs1, v8
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; CHECK-NEXT: li r6, 0
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; CHECK-NEXT: xvmuldp v11, vs2, v14
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; CHECK-NEXT: xvmuldp v3, vs1, v14
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; CHECK-NEXT: xvmuldp vs5, v14, v2
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; CHECK-NEXT: xvmuldp v13, v4, v14
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; CHECK-NEXT: vmr v12, v2
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; CHECK-NEXT: xxlor vs14, v10, v10
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; CHECK-NEXT: xxlor vs0, v2, v2
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; CHECK-NEXT: xxlor vs4, v2, v2
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; CHECK-NEXT: # kill: def $vsrp2 killed $vsrp2 def $uacc1
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; CHECK-NEXT: xxlor vs6, v6, v6
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; CHECK-NEXT: xxlor vs7, v7, v7
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; CHECK-NEXT: xxlor vs8, v12, v12
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; CHECK-NEXT: xxlor vs9, v13, v13
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; CHECK-NEXT: vmr v12, v1
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; CHECK-NEXT: xxlor vs15, v11, v11
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; CHECK-NEXT: vmr v10, v2
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; CHECK-NEXT: xxlor vs1, v3, v3
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; CHECK-NEXT: xxlor vs2, v8, v8
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; CHECK-NEXT: xxlor vs3, v9, v9
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; CHECK-NEXT: xxlor vs10, v12, v12
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; CHECK-NEXT: xxlor vs11, v13, v13
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; CHECK-NEXT: xxmtacc acc1
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; CHECK-NEXT: xxlor vs12, v10, v10
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; CHECK-NEXT: xxlor vs13, v11, v11
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; CHECK-NEXT: xxmtacc acc0
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; CHECK-NEXT: xxmtacc acc2
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; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs0
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; CHECK-NEXT: xxmtacc acc3
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; CHECK-NEXT: xvf64gerpp acc1, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc2, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc3, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc1, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc2, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc3, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc1, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc2, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc3, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc1, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc2, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc3, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc1, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc2, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc3, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc1, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc2, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc3, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc1, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc2, vsp34, vs0
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; CHECK-NEXT: xvf64gerpp acc3, vsp34, vs0
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; CHECK-NEXT: xxmfacc acc0
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; CHECK-NEXT: xxmfacc acc1
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; CHECK-NEXT: xxmfacc acc2
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; CHECK-NEXT: xxmfacc acc3
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; CHECK-NEXT: stxv vs1, 0(r3)
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; CHECK-NEXT: stxv vs9, 32(r3)
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; CHECK-NEXT: stxv vs4, 16(0)
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; CHECK-NEXT: stxv vs12, 48(0)
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; CHECK-NEXT: b .LBB0_1
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;
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; TRACKLIVE-LABEL: acc_regalloc:
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; TRACKLIVE: # %bb.0: # %bb
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; TRACKLIVE-NEXT: lwz r3, 0(r3)
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; TRACKLIVE-NEXT: lxv v4, 0(0)
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; TRACKLIVE-NEXT: xxlxor v0, v0, v0
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; TRACKLIVE-NEXT: xxlxor v1, v1, v1
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; TRACKLIVE-NEXT: stfd f14, -144(r1) # 8-byte Folded Spill
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; TRACKLIVE-NEXT: stfd f15, -136(r1) # 8-byte Folded Spill
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; TRACKLIVE-NEXT: xxlxor v2, v2, v2
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; TRACKLIVE-NEXT: li r6, 1
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; TRACKLIVE-NEXT: li r4, 16
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; TRACKLIVE-NEXT: extswsli r3, r3, 3
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; TRACKLIVE-NEXT: xvmaddadp v1, v4, v1
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; TRACKLIVE-NEXT: lxvdsx v5, 0, r3
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; TRACKLIVE-NEXT: xvmaddadp v0, v5, v0
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; TRACKLIVE-NEXT: .p2align 4
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; TRACKLIVE-NEXT: .LBB0_1: # %bb9
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; TRACKLIVE-NEXT: #
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; TRACKLIVE-NEXT: addi r6, r6, 2
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; TRACKLIVE-NEXT: lxv vs0, 16(0)
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; TRACKLIVE-NEXT: xxlxor vs7, vs7, vs7
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; TRACKLIVE-NEXT: lxv vs1, -64(r5)
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; TRACKLIVE-NEXT: lxv vs4, -16(r5)
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; TRACKLIVE-NEXT: xxlxor vs12, vs12, vs12
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; TRACKLIVE-NEXT: xxlor vs3, v0, v0
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; TRACKLIVE-NEXT: xxlxor vs2, vs2, vs2
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; TRACKLIVE-NEXT: mulld r6, r6, r3
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; TRACKLIVE-NEXT: xxlor vs10, v2, v2
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; TRACKLIVE-NEXT: xxlor vs8, vs10, vs10
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; TRACKLIVE-NEXT: xxlor vs10, v1, v1
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; TRACKLIVE-NEXT: xvmaddadp vs7, vs0, v5
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; TRACKLIVE-NEXT: xvmuldp vs6, vs0, v2
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; TRACKLIVE-NEXT: xvmaddadp vs12, vs4, vs12
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; TRACKLIVE-NEXT: xvmaddadp vs3, vs1, v2
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; TRACKLIVE-NEXT: xvmaddadp vs2, vs1, vs2
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; TRACKLIVE-NEXT: xxlor vs0, v2, v2
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; TRACKLIVE-NEXT: lxvdsx v6, r6, r4
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; TRACKLIVE-NEXT: li r6, 0
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; TRACKLIVE-NEXT: xvmaddadp vs7, v2, v2
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; TRACKLIVE-NEXT: xvmaddadp vs6, v2, v2
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; TRACKLIVE-NEXT: xxlor vs14, vs12, vs12
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; TRACKLIVE-NEXT: xxlor vs12, v2, v2
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; TRACKLIVE-NEXT: xvmuldp v3, vs1, v6
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; TRACKLIVE-NEXT: xvmuldp vs11, v4, v6
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; TRACKLIVE-NEXT: xvmuldp vs13, vs4, v6
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; TRACKLIVE-NEXT: xvmuldp vs5, v6, v2
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; TRACKLIVE-NEXT: xxlor vs4, v2, v2
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; TRACKLIVE-NEXT: xxlor vs1, v3, v3
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; TRACKLIVE-NEXT: xxlor vs9, vs11, vs11
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; TRACKLIVE-NEXT: xxlor vs15, vs13, vs13
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; TRACKLIVE-NEXT: xxmtacc acc1
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; TRACKLIVE-NEXT: xxmtacc acc0
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; TRACKLIVE-NEXT: xxmtacc acc2
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; TRACKLIVE-NEXT: xxmtacc acc3
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; TRACKLIVE-NEXT: xvf64gerpp acc0, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc1, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc2, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc3, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc0, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc1, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc2, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc3, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc0, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc1, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc2, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc3, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc0, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc1, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc2, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc3, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc0, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc1, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc2, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc3, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc0, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc1, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc2, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc3, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc0, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc1, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc2, vsp34, vs0
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; TRACKLIVE-NEXT: xvf64gerpp acc3, vsp34, vs0
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; TRACKLIVE-NEXT: xxmfacc acc0
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; TRACKLIVE-NEXT: xxmfacc acc1
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; TRACKLIVE-NEXT: xxmfacc acc2
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; TRACKLIVE-NEXT: xxmfacc acc3
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; TRACKLIVE-NEXT: stxv vs1, 0(r3)
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; TRACKLIVE-NEXT: stxv vs9, 32(r3)
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; TRACKLIVE-NEXT: stxv vs4, 16(0)
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; TRACKLIVE-NEXT: stxv vs12, 48(0)
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; TRACKLIVE-NEXT: b .LBB0_1
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bb:
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%i = load i32, i32* %arg, align 4
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%i3 = sext i32 %i to i64
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%i4 = shl nsw i64 %i3, 3
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%i5 = bitcast [0 x %0]* %arg1 to i8*
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%i6 = getelementptr i8, i8* %i5, i64 undef
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%i7 = getelementptr [0 x %1], [0 x %1]* %arg2, i64 0, i64 -8
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%i8 = getelementptr i8, i8* %i6, i64 undef
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br label %bb9
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bb9: ; preds = %bb95, %bb
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%i10 = phi i64 [ 1, %bb ], [ 0, %bb95 ]
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%i11 = getelementptr %1, %1* null, i64 2
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%i12 = bitcast %1* %i11 to <2 x double>*
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%i13 = load <2 x double>, <2 x double>* %i12, align 1
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%i14 = add nuw nsw i64 %i10, 2
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%i15 = getelementptr inbounds %1, %1* %i7, i64 undef
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%i16 = bitcast %1* %i15 to <2 x double>*
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%i17 = load <2 x double>, <2 x double>* %i16, align 1
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%i18 = load <2 x double>, <2 x double>* null, align 1
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%i19 = getelementptr %1, %1* %i15, i64 6
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%i20 = bitcast %1* %i19 to <2 x double>*
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%i21 = load <2 x double>, <2 x double>* %i20, align 1
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%i22 = load i64, i64* undef, align 8
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%i23 = insertelement <2 x i64> poison, i64 %i22, i32 0
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%i24 = bitcast <2 x i64> %i23 to <2 x double>
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%i25 = shufflevector <2 x double> %i24, <2 x double> undef, <2 x i32> zeroinitializer
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%i26 = mul i64 %i14, %i4
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%i27 = getelementptr i8, i8* null, i64 %i26
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%i28 = getelementptr inbounds i8, i8* %i27, i64 0
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%i29 = getelementptr i8, i8* %i28, i64 16
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%i30 = bitcast i8* %i29 to i64*
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%i31 = load i64, i64* %i30, align 8
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%i32 = insertelement <2 x i64> poison, i64 %i31, i32 0
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%i33 = bitcast <2 x i64> %i32 to <2 x double>
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%i34 = shufflevector <2 x double> %i33, <2 x double> undef, <2 x i32> zeroinitializer
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%i35 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> zeroinitializer, <2 x double> %i25, <2 x double> zeroinitializer)
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%i36 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> %i13, <2 x double> %i25, <2 x double> zeroinitializer)
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%i37 = fmul contract <2 x double> %i13, zeroinitializer
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%i38 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> %i17, <2 x double> zeroinitializer, <2 x double> %i35)
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%i39 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> zeroinitializer, <2 x double> zeroinitializer, <2 x double> %i36)
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%i40 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> %i17, <2 x double> zeroinitializer, <2 x double> zeroinitializer)
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%i41 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> zeroinitializer, <2 x double> zeroinitializer, <2 x double> %i37)
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%i42 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> %i18, <2 x double> zeroinitializer, <2 x double> zeroinitializer)
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%i43 = tail call contract <2 x double> @llvm.fma.v2f64(<2 x double> %i21, <2 x double> zeroinitializer, <2 x double> zeroinitializer)
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%i44 = fmul contract <2 x double> %i17, %i34
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%i45 = fmul contract <2 x double> zeroinitializer, %i34
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%i46 = fmul contract <2 x double> %i18, %i34
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%i47 = fmul contract <2 x double> %i21, %i34
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%i48 = bitcast <2 x double> %i44 to <16 x i8>
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%i49 = bitcast <2 x double> %i40 to <16 x i8>
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%i50 = bitcast <2 x double> %i38 to <16 x i8>
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%i51 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i48, <16 x i8> %i49, <16 x i8> %i50)
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%i52 = bitcast <2 x double> %i45 to <16 x i8>
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%i53 = bitcast <2 x double> %i41 to <16 x i8>
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%i54 = bitcast <2 x double> %i39 to <16 x i8>
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%i55 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i52, <16 x i8> %i53, <16 x i8> %i54)
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%i56 = bitcast <2 x double> %i46 to <16 x i8>
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%i57 = bitcast <2 x double> %i42 to <16 x i8>
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%i58 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i56, <16 x i8> %i57, <16 x i8> %i56)
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%i59 = bitcast <2 x double> %i47 to <16 x i8>
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%i60 = bitcast <2 x double> %i43 to <16 x i8>
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%i61 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> %i59, <16 x i8> %i60, <16 x i8> %i59)
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%i62 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i51, <256 x i1> undef, <16 x i8> undef)
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%i63 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i55, <256 x i1> undef, <16 x i8> undef)
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%i64 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i58, <256 x i1> undef, <16 x i8> undef)
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%i65 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i61, <256 x i1> undef, <16 x i8> undef)
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%i66 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i62, <256 x i1> undef, <16 x i8> undef)
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%i67 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i63, <256 x i1> undef, <16 x i8> undef)
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%i68 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i64, <256 x i1> undef, <16 x i8> undef)
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%i69 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i65, <256 x i1> undef, <16 x i8> undef)
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%i70 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i66, <256 x i1> undef, <16 x i8> undef)
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%i71 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i67, <256 x i1> undef, <16 x i8> undef)
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%i72 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i68, <256 x i1> undef, <16 x i8> undef)
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%i73 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i69, <256 x i1> undef, <16 x i8> undef)
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%i74 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i70, <256 x i1> undef, <16 x i8> undef)
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%i75 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i71, <256 x i1> undef, <16 x i8> undef)
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%i76 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i72, <256 x i1> undef, <16 x i8> undef)
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%i77 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i73, <256 x i1> undef, <16 x i8> undef)
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%i78 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i74, <256 x i1> undef, <16 x i8> undef)
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%i79 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i75, <256 x i1> undef, <16 x i8> undef)
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%i80 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i76, <256 x i1> undef, <16 x i8> undef)
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%i81 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i77, <256 x i1> undef, <16 x i8> undef)
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br label %bb82
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bb82: ; preds = %bb82, %bb9
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%i83 = phi <512 x i1> [ %i94, %bb82 ], [ %i81, %bb9 ]
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%i84 = phi <512 x i1> [ %i93, %bb82 ], [ %i80, %bb9 ]
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%i85 = phi <512 x i1> [ %i92, %bb82 ], [ %i79, %bb9 ]
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%i86 = phi <512 x i1> [ %i91, %bb82 ], [ %i78, %bb9 ]
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%i87 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i86, <256 x i1> undef, <16 x i8> undef)
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%i88 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i85, <256 x i1> undef, <16 x i8> undef)
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%i89 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i84, <256 x i1> undef, <16 x i8> undef)
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%i90 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i83, <256 x i1> undef, <16 x i8> undef)
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%i91 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i87, <256 x i1> undef, <16 x i8> undef)
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%i92 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i88, <256 x i1> undef, <16 x i8> undef)
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%i93 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i89, <256 x i1> undef, <16 x i8> undef)
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%i94 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %i90, <256 x i1> undef, <16 x i8> undef)
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br i1 undef, label %bb95, label %bb82
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|
|
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bb95: ; preds = %bb82
|
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%i96 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i91)
|
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%i97 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i96, 2
|
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%i98 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i92)
|
|
%i99 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i98, 3
|
|
%i100 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i93)
|
|
%i101 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i100, 2
|
|
%i102 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %i94)
|
|
%i103 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %i102, 3
|
|
%i104 = getelementptr inbounds i8, i8* %i8, i64 undef
|
|
%i105 = bitcast i8* %i104 to <16 x i8>*
|
|
store <16 x i8> %i97, <16 x i8>* %i105, align 1
|
|
%i106 = getelementptr i8, i8* %i104, i64 32
|
|
%i107 = bitcast i8* %i106 to <16 x i8>*
|
|
store <16 x i8> %i101, <16 x i8>* %i107, align 1
|
|
%i108 = getelementptr i8, i8* null, i64 16
|
|
%i109 = bitcast i8* %i108 to <16 x i8>*
|
|
store <16 x i8> %i99, <16 x i8>* %i109, align 1
|
|
%i110 = getelementptr i8, i8* null, i64 48
|
|
%i111 = bitcast i8* %i110 to <16 x i8>*
|
|
store <16 x i8> %i103, <16 x i8>* %i111, align 1
|
|
br label %bb9
|
|
}
|
|
|
|
declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)
|
|
declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
|
|
declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>)
|
|
declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
|
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