ba627a32e1
This patch includes the following updates to the load/store refactoring effort introduced in D93370: - Update various VSX patterns that use to "force" an XForm, to instead just XForm. This allows the ability for the patterns to compute the most optimal addressing mode (and to produce a DForm instruction when possible) - Update pattern and test case for the LXVD2X/STXVD2X intrinsics - Update LIT test cases that use to use the XForm instruction to use the DForm instruction Differential Revision: https://reviews.llvm.org/D95115
75 lines
3.3 KiB
LLVM
75 lines
3.3 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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%class.FullMatrix = type { i8 }
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%class.Vector = type { float* }
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$test = comdat any
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define weak_odr void @test(%class.FullMatrix* %this, %class.Vector* dereferenceable(8) %p1, %class.Vector* dereferenceable(8), i1 zeroext) {
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entry:
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%call = tail call signext i32 @fn1(%class.FullMatrix* %this)
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%cmp10 = icmp sgt i32 %call, 0
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br i1 %cmp10, label %for.body.lr.ph, label %for.cond.cleanup
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for.body.lr.ph: ; preds = %entry
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%val.i = getelementptr inbounds %class.Vector, %class.Vector* %p1, i64 0, i32 0
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%2 = load float*, float** %val.i, align 8
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%wide.trip.count = zext i32 %call to i64
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%min.iters.check = icmp ult i32 %call, 4
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br i1 %min.iters.check, label %for.body.preheader, label %min.iters.checked
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for.body.preheader: ; preds = %middle.block, %min.iters.checked, %for.body.lr.ph
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%indvars.iv.ph = phi i64 [ 0, %min.iters.checked ], [ 0, %for.body.lr.ph ], [ %n.vec, %middle.block ]
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br label %for.body
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min.iters.checked: ; preds = %for.body.lr.ph
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%3 = and i32 %call, 3
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%n.mod.vf = zext i32 %3 to i64
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%n.vec = sub nsw i64 %wide.trip.count, %n.mod.vf
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%cmp.zero = icmp eq i64 %n.vec, 0
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br i1 %cmp.zero, label %for.body.preheader, label %vector.body.preheader
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vector.body.preheader: ; preds = %min.iters.checked
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br label %vector.body
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vector.body: ; preds = %vector.body.preheader, %vector.body
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%index = phi i64 [ %index.next, %vector.body ], [ 0, %vector.body.preheader ]
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%4 = getelementptr inbounds float, float* %2, i64 %index
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%5 = bitcast float* %4 to <4 x float>*
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%wide.load = load <4 x float>, <4 x float>* %5, align 4
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%6 = fpext <4 x float> %wide.load to <4 x ppc_fp128>
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%7 = fadd <4 x ppc_fp128> %6, %6
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%8 = fptrunc <4 x ppc_fp128> %7 to <4 x float>
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%9 = bitcast float* %4 to <4 x float>*
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store <4 x float> %8, <4 x float>* %9, align 4
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%index.next = add i64 %index, 4
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%10 = icmp eq i64 %index.next, %n.vec
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br i1 %10, label %middle.block, label %vector.body
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middle.block: ; preds = %vector.body
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%cmp.n = icmp eq i32 %3, 0
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br i1 %cmp.n, label %for.cond.cleanup, label %for.body.preheader
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for.cond.cleanup.loopexit: ; preds = %for.body
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %middle.block, %entry
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ret void
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for.body: ; preds = %for.body.preheader, %for.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ %indvars.iv.ph, %for.body.preheader ]
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%arrayidx.i = getelementptr inbounds float, float* %2, i64 %indvars.iv
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%11 = load float, float* %arrayidx.i, align 4
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%conv = fpext float %11 to ppc_fp128
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%add = fadd ppc_fp128 %conv, %conv
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%conv4 = fptrunc ppc_fp128 %add to float
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store float %conv4, float* %arrayidx.i, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body
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; CHECK: stfd
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; CHECK: lxvd2x
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}
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declare signext i32 @fn1(%class.FullMatrix*) local_unnamed_addr #1
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