6a06dbafa1
There are some patterns involving the permuted scalar to vector node for which we don't have patterns without direct moves on little endian subtargets. This causes selection errors. While we can of course add the missing patterns, any additional effort to make this work is not useful since there is no support for any CPU that can run in little endian mode and does not support direct moves.
22 lines
903 B
LLVM
22 lines
903 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
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define dso_local void @_Z1jjPiPj() local_unnamed_addr #0 {
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; CHECK-LABEL: _Z1jjPiPj:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld r3, 0(r3)
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; CHECK-NEXT: std r3, -16(r1)
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; CHECK-NEXT: addi r3, r1, -16
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; CHECK-NEXT: lxvd2x vs0, 0, r3
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; CHECK-NEXT: xxswapd v2, vs0
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; CHECK-NEXT: vmrglw v2, v2, v2
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; CHECK-NEXT: xxswapd vs0, v2
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; CHECK-NEXT: stxvd2x vs0, 0, r3
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; CHECK-NEXT: blr
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entry:
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%wide.load42 = load <2 x i32>, <2 x i32>* undef, align 4
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%interleaved.vec49 = shufflevector <2 x i32> %wide.load42, <2 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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store <4 x i32> %interleaved.vec49, <4 x i32>* undef, align 4
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ret void
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}
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