ba627a32e1
This patch includes the following updates to the load/store refactoring effort introduced in D93370: - Update various VSX patterns that use to "force" an XForm, to instead just XForm. This allows the ability for the patterns to compute the most optimal addressing mode (and to produce a DForm instruction when possible) - Update pattern and test case for the LXVD2X/STXVD2X intrinsics - Update LIT test cases that use to use the XForm instruction to use the DForm instruction Differential Revision: https://reviews.llvm.org/D95115
131 lines
5.0 KiB
LLVM
131 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -O3 < %s | FileCheck %s
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; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 \
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; RUN: --implicit-check-not xxswapd
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; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: -mattr=-power9-vector < %s | FileCheck %s --check-prefix=CHECK-P9-NOVECTOR
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; These tests verify that VSX swap optimization works when loading a scalar
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; into a vector register.
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@x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16
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@z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16
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@y = global double 1.780000e+00, align 8
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define void @bar0() {
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; CHECK-LABEL: bar0:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
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; CHECK-NEXT: addis r4, r2, .LC1@toc@ha
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; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
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; CHECK-NEXT: lxvd2x vs0, 0, r3
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; CHECK-NEXT: ld r3, .LC1@toc@l(r4)
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; CHECK-NEXT: xxswapd vs0, vs0
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; CHECK-NEXT: lfd f1, 0(r3)
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; CHECK-NEXT: addis r3, r2, .LC2@toc@ha
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; CHECK-NEXT: ld r3, .LC2@toc@l(r3)
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; CHECK-NEXT: xxmrghd vs0, vs0, vs1
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; CHECK-NEXT: xxswapd vs0, vs0
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; CHECK-NEXT: stxvd2x vs0, 0, r3
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: bar0:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LC0@toc@ha
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; CHECK-P9-NEXT: ld r3, .LC0@toc@l(r3)
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; CHECK-P9-NEXT: lxv vs0, 0(r3)
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; CHECK-P9-NEXT: addis r3, r2, .LC1@toc@ha
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; CHECK-P9-NEXT: ld r3, .LC1@toc@l(r3)
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; CHECK-P9-NEXT: lfd f1, 0(r3)
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; CHECK-P9-NEXT: addis r3, r2, .LC2@toc@ha
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; CHECK-P9-NEXT: ld r3, .LC2@toc@l(r3)
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; CHECK-P9-NEXT: xxmrghd vs0, vs0, vs1
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; CHECK-P9-NEXT: stxv vs0, 0(r3)
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P9-NOVECTOR-LABEL: bar0:
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; CHECK-P9-NOVECTOR: # %bb.0: # %entry
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; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC0@toc@ha
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; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC0@toc@l(r3)
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; CHECK-P9-NOVECTOR-NEXT: lxvd2x vs0, 0, r3
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; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC1@toc@ha
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; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC1@toc@l(r3)
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; CHECK-P9-NOVECTOR-NEXT: xxswapd vs0, vs0
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; CHECK-P9-NOVECTOR-NEXT: lfd f1, 0(r3)
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; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC2@toc@ha
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; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC2@toc@l(r3)
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; CHECK-P9-NOVECTOR-NEXT: xxmrghd vs0, vs0, vs1
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; CHECK-P9-NOVECTOR-NEXT: xxswapd vs0, vs0
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; CHECK-P9-NOVECTOR-NEXT: stxvd2x vs0, 0, r3
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; CHECK-P9-NOVECTOR-NEXT: blr
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entry:
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%0 = load <2 x double>, <2 x double>* @x, align 16
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%1 = load double, double* @y, align 8
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%vecins = insertelement <2 x double> %0, double %1, i32 0
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store <2 x double> %vecins, <2 x double>* @z, align 16
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ret void
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}
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define void @bar1() {
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; CHECK-LABEL: bar1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
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; CHECK-NEXT: addis r4, r2, .LC1@toc@ha
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; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
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; CHECK-NEXT: lxvd2x vs0, 0, r3
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; CHECK-NEXT: ld r3, .LC1@toc@l(r4)
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; CHECK-NEXT: xxswapd vs0, vs0
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; CHECK-NEXT: lfd f1, 0(r3)
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; CHECK-NEXT: addis r3, r2, .LC2@toc@ha
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; CHECK-NEXT: ld r3, .LC2@toc@l(r3)
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; CHECK-NEXT: xxpermdi vs0, vs1, vs0, 1
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; CHECK-NEXT: xxswapd vs0, vs0
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; CHECK-NEXT: stxvd2x vs0, 0, r3
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: bar1:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LC0@toc@ha
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; CHECK-P9-NEXT: ld r3, .LC0@toc@l(r3)
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; CHECK-P9-NEXT: lxv vs0, 0(r3)
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; CHECK-P9-NEXT: addis r3, r2, .LC1@toc@ha
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; CHECK-P9-NEXT: ld r3, .LC1@toc@l(r3)
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; CHECK-P9-NEXT: lfd f1, 0(r3)
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; CHECK-P9-NEXT: addis r3, r2, .LC2@toc@ha
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; CHECK-P9-NEXT: ld r3, .LC2@toc@l(r3)
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; CHECK-P9-NEXT: xxpermdi vs0, vs1, vs0, 1
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; CHECK-P9-NEXT: stxv vs0, 0(r3)
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P9-NOVECTOR-LABEL: bar1:
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; CHECK-P9-NOVECTOR: # %bb.0: # %entry
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; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC0@toc@ha
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; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC0@toc@l(r3)
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; CHECK-P9-NOVECTOR-NEXT: lxvd2x vs0, 0, r3
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; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC1@toc@ha
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; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC1@toc@l(r3)
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; CHECK-P9-NOVECTOR-NEXT: xxswapd vs0, vs0
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; CHECK-P9-NOVECTOR-NEXT: lfd f1, 0(r3)
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; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC2@toc@ha
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; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC2@toc@l(r3)
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; CHECK-P9-NOVECTOR-NEXT: xxpermdi vs0, vs1, vs0, 1
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; CHECK-P9-NOVECTOR-NEXT: xxswapd vs0, vs0
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; CHECK-P9-NOVECTOR-NEXT: stxvd2x vs0, 0, r3
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; CHECK-P9-NOVECTOR-NEXT: blr
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entry:
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%0 = load <2 x double>, <2 x double>* @x, align 16
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%1 = load double, double* @y, align 8
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%vecins = insertelement <2 x double> %0, double %1, i32 1
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store <2 x double> %vecins, <2 x double>* @z, align 16
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ret void
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}
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