ba627a32e1
This patch includes the following updates to the load/store refactoring effort introduced in D93370: - Update various VSX patterns that use to "force" an XForm, to instead just XForm. This allows the ability for the patterns to compute the most optimal addressing mode (and to produce a DForm instruction when possible) - Update pattern and test case for the LXVD2X/STXVD2X intrinsics - Update LIT test cases that use to use the XForm instruction to use the DForm instruction Differential Revision: https://reviews.llvm.org/D95115
116 lines
3.7 KiB
LLVM
116 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -ppc-convert-rr-to-ri=false -ppc-asm-full-reg-names < %s | FileCheck %s
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; ISEL matches address mode xaddr.
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define i8 @test_xaddr(i8* %p) {
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; CHECK-LABEL: test_xaddr:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li r4, 0
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; CHECK-NEXT: std r3, -8(r1)
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; CHECK-NEXT: ori r4, r4, 40000
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; CHECK-NEXT: lbzx r3, r3, r4
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; CHECK-NEXT: blr
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entry:
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%p.addr = alloca i8*, align 8
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store i8* %p, i8** %p.addr, align 8
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%0 = load i8*, i8** %p.addr, align 8
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%add.ptr = getelementptr inbounds i8, i8* %0, i64 40000
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%1 = load i8, i8* %add.ptr, align 1
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ret i8 %1
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}
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; ISEL matches address mode xaddrX4.
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define i64 @test_xaddrX4(i8* %p) {
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; CHECK-LABEL: test_xaddrX4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li r4, 3
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; CHECK-NEXT: std r3, -8(r1)
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; CHECK-NEXT: ldx r3, r3, r4
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; CHECK-NEXT: blr
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entry:
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%p.addr = alloca i8*, align 8
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store i8* %p, i8** %p.addr, align 8
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%0 = load i8*, i8** %p.addr, align 8
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%add.ptr = getelementptr inbounds i8, i8* %0, i64 3
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%1 = bitcast i8* %add.ptr to i64*
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%2 = load i64, i64* %1, align 8
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ret i64 %2
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}
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; ISEL matches address mode xaddrX16.
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define <2 x double> @test_xaddrX16(double* %arr) {
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; CHECK-LABEL: test_xaddrX16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li r4, 40
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; CHECK-NEXT: lxvx vs34, r3, r4
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; CHECK-NEXT: blr
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entry:
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%arrayidx1 = getelementptr inbounds double, double* %arr, i64 5
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%0 = bitcast double* %arrayidx1 to <2 x double>*
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%1 = load <2 x double>, <2 x double>* %0, align 16
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ret <2 x double> %1
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}
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; ISEL matches address mode xoaddr.
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define void @test_xoaddr(i32* %arr, i32* %arrTo) {
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; CHECK-LABEL: test_xoaddr:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li r5, 8
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; CHECK-NEXT: lxvx vs0, r3, r5
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; CHECK-NEXT: li r3, 4
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; CHECK-NEXT: stxvx vs0, r4, r3
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; CHECK-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds i32, i32* %arrTo, i64 1
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%0 = bitcast i32* %arrayidx to <4 x i32>*
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%arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
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%1 = bitcast i32* %arrayidx1 to <4 x i32>*
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%2 = load <4 x i32>, <4 x i32>* %1, align 8
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store <4 x i32> %2, <4 x i32>* %0, align 8
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ret void
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}
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; ISEL matches address mode xaddrX4 and generates LI which can be moved outside of
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; loop.
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define i64 @test_xaddrX4_loop(i8* %p) {
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; CHECK-LABEL: test_xaddrX4_loop:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi r4, r3, -8
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; CHECK-NEXT: li r3, 8
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; CHECK-NEXT: li r5, 3
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; CHECK-NEXT: mtctr r3
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; CHECK-NEXT: li r3, 0
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB4_1: # %for.body
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; CHECK-NEXT: #
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; CHECK-NEXT: ldu r6, 8(r4)
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; CHECK-NEXT: ldx r7, r4, r5
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; CHECK-NEXT: maddld r3, r7, r6, r3
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; CHECK-NEXT: bdnz .LBB4_1
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; CHECK-NEXT: # %bb.2: # %for.end
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; CHECK-NEXT: blr
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; loop instruction number is changed from 5 to 4, so its align is changed from 5 to 4.
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%i.015 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
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%res.014 = phi i64 [ 0, %entry ], [ %add, %for.body ]
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%mul = shl i64 %i.015, 3
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%add.ptr = getelementptr inbounds i8, i8* %p, i64 %mul
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%0 = bitcast i8* %add.ptr to i64*
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%1 = load i64, i64* %0, align 8
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%add.ptr3 = getelementptr inbounds i8, i8* %add.ptr, i64 3
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%2 = bitcast i8* %add.ptr3 to i64*
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%3 = load i64, i64* %2, align 8
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%mul4 = mul i64 %3, %1
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%add = add i64 %mul4, %res.014
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%inc = add nuw nsw i64 %i.015, 1
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%exitcond = icmp eq i64 %inc, 8
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret i64 %add
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}
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