ba627a32e1
This patch includes the following updates to the load/store refactoring effort introduced in D93370: - Update various VSX patterns that use to "force" an XForm, to instead just XForm. This allows the ability for the patterns to compute the most optimal addressing mode (and to produce a DForm instruction when possible) - Update pattern and test case for the LXVD2X/STXVD2X intrinsics - Update LIT test cases that use to use the XForm instruction to use the DForm instruction Differential Revision: https://reviews.llvm.org/D95115
205 lines
5.6 KiB
LLVM
205 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE
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define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) {
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; CHECK-LE-LABEL: test1:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: vextubrx 3, 5, 2
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; CHECK-LE-NEXT: clrldi 3, 3, 56
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test1:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vextublx 3, 5, 2
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; CHECK-BE-NEXT: clrldi 3, 3, 56
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <16 x i8> %a, i32 %index
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ret i8 %vecext
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}
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define signext i8 @test2(<16 x i8> %a, i32 signext %index) {
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; CHECK-LE-LABEL: test2:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: vextubrx 3, 5, 2
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; CHECK-LE-NEXT: extsb 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test2:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vextublx 3, 5, 2
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; CHECK-BE-NEXT: extsb 3, 3
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <16 x i8> %a, i32 %index
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ret i8 %vecext
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}
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define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) {
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; CHECK-LE-LABEL: test3:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30
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; CHECK-LE-NEXT: vextuhrx 3, 3, 2
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; CHECK-LE-NEXT: clrldi 3, 3, 48
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test3:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30
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; CHECK-BE-NEXT: vextuhlx 3, 3, 2
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; CHECK-BE-NEXT: clrldi 3, 3, 48
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <8 x i16> %a, i32 %index
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ret i16 %vecext
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}
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define signext i16 @test4(<8 x i16> %a, i32 signext %index) {
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; CHECK-LE-LABEL: test4:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30
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; CHECK-LE-NEXT: vextuhrx 3, 3, 2
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; CHECK-LE-NEXT: extsh 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test4:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30
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; CHECK-BE-NEXT: vextuhlx 3, 3, 2
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; CHECK-BE-NEXT: extsh 3, 3
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <8 x i16> %a, i32 %index
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ret i16 %vecext
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}
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define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) {
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; CHECK-LE-LABEL: test5:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29
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; CHECK-LE-NEXT: vextuwrx 3, 3, 2
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test5:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29
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; CHECK-BE-NEXT: vextuwlx 3, 3, 2
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %a, i32 %index
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ret i32 %vecext
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}
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define signext i32 @test6(<4 x i32> %a, i32 signext %index) {
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; CHECK-LE-LABEL: test6:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29
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; CHECK-LE-NEXT: vextuwrx 3, 3, 2
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; CHECK-LE-NEXT: extsw 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test6:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29
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; CHECK-BE-NEXT: vextuwlx 3, 3, 2
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; CHECK-BE-NEXT: extsw 3, 3
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %a, i32 %index
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ret i32 %vecext
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}
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; Test with immediate index
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define zeroext i8 @test7(<16 x i8> %a) {
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; CHECK-LE-LABEL: test7:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: li 3, 1
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; CHECK-LE-NEXT: vextubrx 3, 3, 2
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; CHECK-LE-NEXT: clrldi 3, 3, 56
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test7:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li 3, 1
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; CHECK-BE-NEXT: vextublx 3, 3, 2
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; CHECK-BE-NEXT: clrldi 3, 3, 56
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <16 x i8> %a, i32 1
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ret i8 %vecext
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}
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define zeroext i16 @test8(<8 x i16> %a) {
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; CHECK-LE-LABEL: test8:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: li 3, 2
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; CHECK-LE-NEXT: vextuhrx 3, 3, 2
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; CHECK-LE-NEXT: clrldi 3, 3, 48
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test8:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li 3, 2
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; CHECK-BE-NEXT: vextuhlx 3, 3, 2
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; CHECK-BE-NEXT: clrldi 3, 3, 48
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <8 x i16> %a, i32 1
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ret i16 %vecext
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}
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define zeroext i32 @test9(<4 x i32> %a) {
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; CHECK-LE-LABEL: test9:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: li 3, 12
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; CHECK-LE-NEXT: vextuwrx 3, 3, 2
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test9:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li 3, 12
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; CHECK-BE-NEXT: vextuwlx 3, 3, 2
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %a, i32 3
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ret i32 %vecext
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}
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define double @test10(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LE-LABEL: test10:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: addis 3, 2, .LCPI9_0@toc@ha
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; CHECK-LE-NEXT: addi 3, 3, .LCPI9_0@toc@l
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; CHECK-LE-NEXT: lxv 36, 0(3)
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; CHECK-LE-NEXT: addis 3, 2, .LCPI9_1@toc@ha
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; CHECK-LE-NEXT: lfs 0, .LCPI9_1@toc@l(3)
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; CHECK-LE-NEXT: vperm 2, 3, 2, 4
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; CHECK-LE-NEXT: xsadddp 1, 34, 0
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test10:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addis 3, 2, .LCPI9_0@toc@ha
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; CHECK-BE-NEXT: vmrghw 3, 3, 2
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; CHECK-BE-NEXT: lfs 0, .LCPI9_0@toc@l(3)
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; CHECK-BE-NEXT: vmrglw 2, 3, 2
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; CHECK-BE-NEXT: xsadddp 1, 34, 0
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; CHECK-BE-NEXT: blr
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entry:
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%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 2, i32 3, i32 7>
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%cast = bitcast <4 x i32> %shuffle to <2 x double>
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%extract = extractelement <2 x double> %cast, i32 0
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%add = fadd double %extract, 1.0000
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ret double %add
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}
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