ba627a32e1
This patch includes the following updates to the load/store refactoring effort introduced in D93370: - Update various VSX patterns that use to "force" an XForm, to instead just XForm. This allows the ability for the patterns to compute the most optimal addressing mode (and to produce a DForm instruction when possible) - Update pattern and test case for the LXVD2X/STXVD2X intrinsics - Update LIT test cases that use to use the XForm instruction to use the DForm instruction Differential Revision: https://reviews.llvm.org/D95115
212 lines
6.9 KiB
LLVM
212 lines
6.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr9 \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,CHECK-P9
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,CHECK-NOINTRIN
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,CHECK-NOINTRIN
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 \
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; RUN: -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,CHECK-P9
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector \
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; RUN: -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,CHECK-INTRIN
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \
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; RUN: -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,CHECK-INTRIN
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; Function Attrs: nounwind readnone
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define <4 x i32> @test1(i8* %a) {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvw4x v2, 0, r3
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %a)
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ret <4 x i32> %0
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}
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8*)
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; Function Attrs: nounwind readnone
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define <2 x double> @test2(i8* %a) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvd2x v2, 0, r3
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %a)
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ret <2 x double> %0
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}
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; Function Attrs: nounwind readnone
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declare <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8*)
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; Function Attrs: nounwind readnone
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define void @test3(<4 x i32> %a, i8* %b) {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stxvw4x v2, 0, r5
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; CHECK-NEXT: blr
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entry:
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tail call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %a, i8* %b)
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ret void
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}
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; Function Attrs: nounwind readnone
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declare void @llvm.ppc.vsx.stxvw4x.be(<4 x i32>, i8*)
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; Function Attrs: nounwind readnone
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define void @test4(<2 x double> %a, i8* %b) {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stxvd2x v2, 0, r5
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; CHECK-NEXT: blr
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entry:
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tail call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %a, i8* %b)
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ret void
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}
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; Function Attrs: nounwind readnone
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declare void @llvm.ppc.vsx.stxvd2x.be(<2 x double>, i8*)
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define i32 @test_vec_test_swdiv(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: test_vec_test_swdiv:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvtdivdp cr0, v2, v3
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; CHECK-NEXT: mfocrf r3, 128
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; CHECK-NEXT: srwi r3, r3, 28
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b)
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ret i32 %0
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}
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declare i32 @llvm.ppc.vsx.xvtdivdp(<2 x double>, <2 x double>)
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define i32 @test_vec_test_swdivs(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test_vec_test_swdivs:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvtdivsp cr0, v2, v3
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; CHECK-NEXT: mfocrf r3, 128
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; CHECK-NEXT: srwi r3, r3, 28
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.vsx.xvtdivsp(<4 x float> %a, <4 x float> %b)
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ret i32 %0
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}
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declare i32 @llvm.ppc.vsx.xvtdivsp(<4 x float>, <4 x float>)
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define i32 @test_vec_test_swsqrt(<2 x double> %a) {
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; CHECK-LABEL: test_vec_test_swsqrt:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvtsqrtdp cr0, v2
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; CHECK-NEXT: mfocrf r3, 128
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; CHECK-NEXT: srwi r3, r3, 28
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %a)
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ret i32 %0
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}
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declare i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double>)
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define i32 @test_vec_test_swsqrts(<4 x float> %a) {
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; CHECK-LABEL: test_vec_test_swsqrts:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvtsqrtsp cr0, v2
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; CHECK-NEXT: mfocrf r3, 128
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; CHECK-NEXT: srwi r3, r3, 28
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.vsx.xvtsqrtsp(<4 x float> %a)
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ret i32 %0
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}
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declare i32 @llvm.ppc.vsx.xvtsqrtsp(<4 x float>)
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define i32 @xvtdivdp_andi(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: xvtdivdp_andi:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvtdivdp cr0, v2, v3
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; CHECK-NEXT: li r4, 222
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; CHECK-NEXT: mfocrf r3, 128
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; CHECK-NEXT: srwi r3, r3, 28
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; CHECK-NEXT: andi. r3, r3, 2
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; CHECK-NEXT: li r3, 22
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; CHECK-NEXT: iseleq r3, r4, r3
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b)
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%1 = and i32 %0, 2
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%cmp.not = icmp eq i32 %1, 0
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%retval.0 = select i1 %cmp.not, i32 222, i32 22
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ret i32 %retval.0
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}
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define i32 @xvtdivdp_shift(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: xvtdivdp_shift:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvtdivdp cr0, v2, v3
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; CHECK-NEXT: mfocrf r3, 128
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; CHECK-NEXT: srwi r3, r3, 28
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; CHECK-NEXT: rlwinm r3, r3, 28, 31, 31
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b)
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%1 = lshr i32 %0, 4
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%.lobit = and i32 %1, 1
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ret i32 %.lobit
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}
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; Function Attrs: nounwind readnone
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define <2 x double> @test_lxvd2x(i8* %a) {
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; CHECK-P9-LABEL: test_lxvd2x:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: lxv v2, 0(r3)
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; CHECK-P9-NEXT: blr
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;
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; CHECK-NOINTRIN-LABEL: test_lxvd2x:
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; CHECK-NOINTRIN: # %bb.0: # %entry
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; CHECK-NOINTRIN-NEXT: lxvd2x vs0, 0, r3
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; CHECK-NOINTRIN-NEXT: xxswapd v2, vs0
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; CHECK-NOINTRIN-NEXT: blr
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;
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; CHECK-INTRIN-LABEL: test_lxvd2x:
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; CHECK-INTRIN: # %bb.0: # %entry
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; CHECK-INTRIN-NEXT: lxvd2x v2, 0, r3
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; CHECK-INTRIN-NEXT: blr
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entry:
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%0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %a)
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ret <2 x double> %0
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}
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; Function Attrs: nounwind readnone
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declare <2 x double> @llvm.ppc.vsx.lxvd2x(i8*)
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; Function Attrs: nounwind readnone
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define void @test_stxvd2x(<2 x double> %a, i8* %b) {
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; CHECK-P9-LABEL: test_stxvd2x:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: stxv v2, 0(r5)
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; CHECK-P9-NEXT: blr
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;
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; CHECK-NOINTRIN-LABEL: test_stxvd2x:
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; CHECK-NOINTRIN: # %bb.0: # %entry
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; CHECK-NOINTRIN-NEXT: xxswapd vs0, v2
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; CHECK-NOINTRIN-NEXT: stxvd2x vs0, 0, r5
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; CHECK-NOINTRIN-NEXT: blr
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;
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; CHECK-INTRIN-LABEL: test_stxvd2x:
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; CHECK-INTRIN: # %bb.0: # %entry
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; CHECK-INTRIN-NEXT: stxvd2x v2, 0, r5
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; CHECK-INTRIN-NEXT: blr
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entry:
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tail call void @llvm.ppc.vsx.stxvd2x(<2 x double> %a, i8* %b)
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ret void
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}
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; Function Attrs: nounwind readnone
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declare void @llvm.ppc.vsx.stxvd2x(<2 x double>, i8*)
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