81efb82570
If we need to shift left anyway we might be able to take advantage of LUI implicitly shifting its immediate left by 12 to cover part of the shift. This allows us to use more bits of the LUI immediate to avoid an ADDI. isDesirableToCommuteWithShift now considers compressed instruction opportunities when deciding if commuting should be allowed. I believe this is the same or similar to one of the optimizations from D79492. Reviewed By: luismarques, arcbbb Differential Revision: https://reviews.llvm.org/D105417
263 lines
8.4 KiB
LLVM
263 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IFD %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IFD %s
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define dso_local double @fld(double *%a) nounwind {
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; RV32IFD-LABEL: fld:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: fld ft0, 0(a0)
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; RV32IFD-NEXT: fld ft1, 24(a0)
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; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fld:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fld ft0, 0(a0)
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; RV64IFD-NEXT: fld ft1, 24(a0)
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; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ret
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%1 = load double, double* %a
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%2 = getelementptr double, double* %a, i32 3
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%3 = load double, double* %2
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; Use both loaded values in an FP op to ensure an fld is used, even for the
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; soft float ABI
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%4 = fadd double %1, %3
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ret double %4
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}
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define dso_local void @fsd(double *%a, double %b, double %c) nounwind {
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; RV32IFD-LABEL: fsd:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a3, 8(sp)
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; RV32IFD-NEXT: sw a4, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a1, 8(sp)
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; RV32IFD-NEXT: sw a2, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
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; RV32IFD-NEXT: fsd ft0, 0(a0)
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; RV32IFD-NEXT: fsd ft0, 64(a0)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fsd:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a2
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; RV64IFD-NEXT: fmv.d.x ft1, a1
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; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
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; RV64IFD-NEXT: fsd ft0, 0(a0)
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; RV64IFD-NEXT: fsd ft0, 64(a0)
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; RV64IFD-NEXT: ret
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; Use %b and %c in an FP op to ensure floating point registers are used, even
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; for the soft float ABI
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%1 = fadd double %b, %c
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store double %1, double* %a
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%2 = getelementptr double, double* %a, i32 8
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store double %1, double* %2
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ret void
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}
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; Check load and store to a global
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@G = dso_local global double 0.0
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define dso_local double @fld_fsd_global(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fld_fsd_global:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
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; RV32IFD-NEXT: lui a0, %hi(G)
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; RV32IFD-NEXT: fld ft1, %lo(G)(a0)
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; RV32IFD-NEXT: fsd ft0, %lo(G)(a0)
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; RV32IFD-NEXT: addi a0, a0, %lo(G)
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; RV32IFD-NEXT: fld ft1, 72(a0)
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; RV32IFD-NEXT: fsd ft0, 72(a0)
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fld_fsd_global:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
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; RV64IFD-NEXT: lui a0, %hi(G)
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; RV64IFD-NEXT: fld ft1, %lo(G)(a0)
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; RV64IFD-NEXT: fsd ft0, %lo(G)(a0)
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; RV64IFD-NEXT: addi a1, a0, %lo(G)
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; RV64IFD-NEXT: fld ft1, 72(a1)
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: fsd ft0, 72(a1)
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; RV64IFD-NEXT: ret
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; Use %a and %b in an FP op to ensure floating point registers are used, even
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; for the soft float ABI
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%1 = fadd double %a, %b
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%2 = load volatile double, double* @G
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store double %1, double* @G
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%3 = getelementptr double, double* @G, i32 9
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%4 = load volatile double, double* %3
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store double %1, double* %3
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ret double %1
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}
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; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
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define dso_local double @fld_fsd_constant(double %a) nounwind {
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; RV32IFD-LABEL: fld_fsd_constant:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: lui a0, 912092
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; RV32IFD-NEXT: fld ft1, -273(a0)
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; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
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; RV32IFD-NEXT: fsd ft0, -273(a0)
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fld_fsd_constant:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: lui a1, 228023
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; RV64IFD-NEXT: slli a1, a1, 2
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; RV64IFD-NEXT: fld ft0, -273(a1)
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: fsd ft0, -273(a1)
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; RV64IFD-NEXT: ret
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%1 = inttoptr i32 3735928559 to double*
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%2 = load volatile double, double* %1
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%3 = fadd double %a, %2
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store double %3, double* %1
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ret double %3
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}
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declare void @notdead(i8*)
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define dso_local double @fld_stack(double %a) nounwind {
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; RV32IFD-LABEL: fld_stack:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -32
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; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill
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; RV32IFD-NEXT: addi a0, sp, 16
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; RV32IFD-NEXT: call notdead@plt
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; RV32IFD-NEXT: fld ft0, 16(sp)
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; RV32IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload
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; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
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; RV32IFD-NEXT: addi sp, sp, 32
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fld_stack:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: addi sp, sp, -32
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; RV64IFD-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
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; RV64IFD-NEXT: fmv.d.x ft0, a0
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; RV64IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
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; RV64IFD-NEXT: addi a0, sp, 16
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; RV64IFD-NEXT: call notdead@plt
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; RV64IFD-NEXT: fld ft0, 16(sp)
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; RV64IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload
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; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
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; RV64IFD-NEXT: addi sp, sp, 32
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; RV64IFD-NEXT: ret
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%1 = alloca double, align 8
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%2 = bitcast double* %1 to i8*
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call void @notdead(i8* %2)
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%3 = load double, double* %1
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%4 = fadd double %3, %a ; force load in to FPR64
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ret double %4
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}
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define dso_local void @fsd_stack(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fsd_stack:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -32
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; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
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; RV32IFD-NEXT: fsd ft0, 16(sp)
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; RV32IFD-NEXT: addi a0, sp, 16
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; RV32IFD-NEXT: call notdead@plt
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; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
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; RV32IFD-NEXT: addi sp, sp, 32
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fsd_stack:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: addi sp, sp, -16
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; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
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; RV64IFD-NEXT: fsd ft0, 0(sp)
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; RV64IFD-NEXT: mv a0, sp
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; RV64IFD-NEXT: call notdead@plt
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; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IFD-NEXT: addi sp, sp, 16
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; RV64IFD-NEXT: ret
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%1 = fadd double %a, %b ; force store from FPR64
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%2 = alloca double, align 8
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store double %1, double* %2
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%3 = bitcast double* %2 to i8*
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call void @notdead(i8* %3)
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ret void
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}
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; Test selection of store<ST4[%a], trunc to f32>, ..
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define dso_local void @fsd_trunc(float* %a, double %b) nounwind noinline optnone {
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; RV32IFD-LABEL: fsd_trunc:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a1, 8(sp)
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; RV32IFD-NEXT: sw a2, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: fcvt.s.d ft0, ft0
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; RV32IFD-NEXT: fsw ft0, 0(a0)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fsd_trunc:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fcvt.s.d ft0, ft0
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; RV64IFD-NEXT: fsw ft0, 0(a0)
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; RV64IFD-NEXT: ret
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%1 = fptrunc double %b to float
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store float %1, float* %a, align 4
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ret void
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}
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