81efb82570
If we need to shift left anyway we might be able to take advantage of LUI implicitly shifting its immediate left by 12 to cover part of the shift. This allows us to use more bits of the LUI immediate to avoid an ADDI. isDesirableToCommuteWithShift now considers compressed instruction opportunities when deciding if commuting should be allowed. I believe this is the same or similar to one of the optimizations from D79492. Reviewed By: luismarques, arcbbb Differential Revision: https://reviews.llvm.org/D105417
207 lines
6.5 KiB
LLVM
207 lines
6.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IF %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IF %s
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define dso_local float @flw(float *%a) nounwind {
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; RV32IF-LABEL: flw:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: flw ft0, 0(a0)
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; RV32IF-NEXT: flw ft1, 12(a0)
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; RV32IF-NEXT: fadd.s ft0, ft0, ft1
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: flw:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: flw ft0, 0(a0)
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; RV64IF-NEXT: flw ft1, 12(a0)
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; RV64IF-NEXT: fadd.s ft0, ft0, ft1
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = load float, float* %a
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%2 = getelementptr float, float* %a, i32 3
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%3 = load float, float* %2
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; Use both loaded values in an FP op to ensure an flw is used, even for the
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; soft float ABI
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%4 = fadd float %1, %3
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ret float %4
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}
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define dso_local void @fsw(float *%a, float %b, float %c) nounwind {
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; Use %b and %c in an FP op to ensure floating point registers are used, even
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; for the soft float ABI
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; RV32IF-LABEL: fsw:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a2
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; RV32IF-NEXT: fmv.w.x ft1, a1
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fsw ft0, 0(a0)
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; RV32IF-NEXT: fsw ft0, 32(a0)
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fsw:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a2
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; RV64IF-NEXT: fmv.w.x ft1, a1
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; RV64IF-NEXT: fadd.s ft0, ft1, ft0
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; RV64IF-NEXT: fsw ft0, 0(a0)
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; RV64IF-NEXT: fsw ft0, 32(a0)
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; RV64IF-NEXT: ret
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%1 = fadd float %b, %c
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store float %1, float* %a
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%2 = getelementptr float, float* %a, i32 8
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store float %1, float* %2
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ret void
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}
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; Check load and store to a global
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@G = dso_local global float 0.0
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define dso_local float @flw_fsw_global(float %a, float %b) nounwind {
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; Use %a and %b in an FP op to ensure floating point registers are used, even
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; for the soft float ABI
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; RV32IF-LABEL: flw_fsw_global:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: lui a0, %hi(G)
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; RV32IF-NEXT: flw ft1, %lo(G)(a0)
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; RV32IF-NEXT: fsw ft0, %lo(G)(a0)
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; RV32IF-NEXT: addi a1, a0, %lo(G)
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; RV32IF-NEXT: flw ft1, 36(a1)
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: fsw ft0, 36(a1)
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: flw_fsw_global:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fadd.s ft0, ft1, ft0
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; RV64IF-NEXT: lui a0, %hi(G)
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; RV64IF-NEXT: flw ft1, %lo(G)(a0)
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; RV64IF-NEXT: fsw ft0, %lo(G)(a0)
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; RV64IF-NEXT: addi a1, a0, %lo(G)
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; RV64IF-NEXT: flw ft1, 36(a1)
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: fsw ft0, 36(a1)
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; RV64IF-NEXT: ret
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%1 = fadd float %a, %b
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%2 = load volatile float, float* @G
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store float %1, float* @G
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%3 = getelementptr float, float* @G, i32 9
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%4 = load volatile float, float* %3
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store float %1, float* %3
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ret float %1
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}
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; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
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define dso_local float @flw_fsw_constant(float %a) nounwind {
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; RV32IF-LABEL: flw_fsw_constant:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: lui a1, 912092
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; RV32IF-NEXT: flw ft0, -273(a1)
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: fsw ft0, -273(a1)
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: flw_fsw_constant:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: lui a1, 228023
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; RV64IF-NEXT: slli a1, a1, 2
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; RV64IF-NEXT: flw ft0, -273(a1)
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fadd.s ft0, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: fsw ft0, -273(a1)
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; RV64IF-NEXT: ret
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%1 = inttoptr i32 3735928559 to float*
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%2 = load volatile float, float* %1
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%3 = fadd float %a, %2
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store float %3, float* %1
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ret float %3
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}
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declare void @notdead(i8*)
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define dso_local float @flw_stack(float %a) nounwind {
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; RV32IF-LABEL: flw_stack:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: addi a0, sp, 8
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; RV32IF-NEXT: call notdead@plt
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; RV32IF-NEXT: flw ft0, 8(sp)
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; RV32IF-NEXT: flw ft1, 4(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: fadd.s ft0, ft0, ft1
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: flw_stack:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: addi sp, sp, -16
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; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fsw ft0, 0(sp) # 4-byte Folded Spill
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; RV64IF-NEXT: addi a0, sp, 4
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; RV64IF-NEXT: call notdead@plt
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; RV64IF-NEXT: flw ft0, 4(sp)
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; RV64IF-NEXT: flw ft1, 0(sp) # 4-byte Folded Reload
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; RV64IF-NEXT: fadd.s ft0, ft0, ft1
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IF-NEXT: addi sp, sp, 16
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; RV64IF-NEXT: ret
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%1 = alloca float, align 4
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%2 = bitcast float* %1 to i8*
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call void @notdead(i8* %2)
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%3 = load float, float* %1
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%4 = fadd float %3, %a ; force load in to FPR32
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ret float %4
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}
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define dso_local void @fsw_stack(float %a, float %b) nounwind {
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; RV32IF-LABEL: fsw_stack:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fsw ft0, 8(sp)
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; RV32IF-NEXT: addi a0, sp, 8
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; RV32IF-NEXT: call notdead@plt
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; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fsw_stack:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: addi sp, sp, -16
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; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fadd.s ft0, ft1, ft0
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; RV64IF-NEXT: fsw ft0, 4(sp)
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; RV64IF-NEXT: addi a0, sp, 4
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; RV64IF-NEXT: call notdead@plt
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; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IF-NEXT: addi sp, sp, 16
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; RV64IF-NEXT: ret
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%1 = fadd float %a, %b ; force store from FPR32
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%2 = alloca float, align 4
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store float %1, float* %2
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%3 = bitcast float* %2 to i8*
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call void @notdead(i8* %3)
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ret void
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}
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