88bc29f5f2
Previously we converted ISD condition codes to integers and stored them directly in our MIR instructions. The ISD enum kind of belongs to SelectionDAG so that seems like incorrect layering. This patch instead uses a CondCode node on RISCV::SELECT_CC until isel and then converts it from ISD encoding to a RISCV specific value. This value can be converted to/from the RISCV branch opcodes in the RISCV namespace. My larger motivation is to possibly support a microarchitectural feature of some CPUs where a short forward branch over a single instruction can be predicated internally. This will require a new pseudo instruction for select that needs to carry a branch condition and live probably until RISCVExpandPseudos. At that point it can be expanded to control flow without other instructions ending up in the predicated basic block. Using an ISD encoding in RISCVExpandPseudos doesn't seem like correct layering. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D107400
281 lines
11 KiB
YAML
281 lines
11 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -run-pass=finalize-isel -simplify-mir -o - %s \
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# RUN: | FileCheck -check-prefix=RV32I %s
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# RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -run-pass=finalize-isel -simplify-mir -o - %s \
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# RUN: | FileCheck -check-prefix=RV32IBT %s
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# RUN: llc -mtriple=riscv64 -run-pass=finalize-isel -simplify-mir -o - %s \
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# RUN: | FileCheck -check-prefix=RV64I %s
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# RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -run-pass=finalize-isel -simplify-mir -o - %s \
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# RUN: | FileCheck -check-prefix=RV64IBT %s
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# Provide dummy definitions of functions and just enough metadata to create a
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# DBG_VALUE.
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--- |
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define void @cmov_interleaved_bad() {
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ret void
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}
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define void @cmov_interleaved_debug_value() {
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ret void
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}
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...
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---
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# Here we have a sequence of select instructions with a non-select instruction
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# in the middle. Because the non-select depends on the result of a previous
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# select, we cannot optimize the sequence to share control-flow.
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name: cmov_interleaved_bad
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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- { id: 6, class: gpr }
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- { id: 7, class: gpr }
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- { id: 8, class: gpr }
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- { id: 9, class: gpr }
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- { id: 10, class: gpr }
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liveins:
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- { reg: '$x10', virtual-reg: '%0' }
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- { reg: '$x11', virtual-reg: '%1' }
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- { reg: '$x12', virtual-reg: '%2' }
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- { reg: '$x13', virtual-reg: '%3' }
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body: |
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bb.0:
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liveins: $x10, $x11, $x12, $x13
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; RV32I-LABEL: name: cmov_interleaved_bad
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; RV32I: successors: %bb.1, %bb.2
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; RV32I: liveins: $x10, $x11, $x12, $x13
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; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x13
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; RV32I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
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; RV32I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
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; RV32I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
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; RV32I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
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; RV32I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
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; RV32I: BNE [[ANDI]], [[COPY4]], %bb.2
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; RV32I: .1:
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; RV32I: .2:
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; RV32I: successors: %bb.3, %bb.4
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; RV32I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
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; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
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; RV32I: BNE [[ANDI]], [[COPY4]], %bb.4
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; RV32I: .3:
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; RV32I: .4:
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; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
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; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
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; RV32I: $x10 = COPY [[ADD]]
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; RV32I: PseudoRET implicit $x10
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; RV32IBT-LABEL: name: cmov_interleaved_bad
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; RV32IBT: successors: %bb.1, %bb.2
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; RV32IBT: liveins: $x10, $x11, $x12, $x13
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; RV32IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13
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; RV32IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
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; RV32IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
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; RV32IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
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; RV32IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
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; RV32IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
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; RV32IBT: BNE [[ANDI]], [[COPY4]], %bb.2
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; RV32IBT: .1:
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; RV32IBT: .2:
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; RV32IBT: successors: %bb.3, %bb.4
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; RV32IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
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; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
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; RV32IBT: BNE [[ANDI]], [[COPY4]], %bb.4
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; RV32IBT: .3:
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; RV32IBT: .4:
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; RV32IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
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; RV32IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
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; RV32IBT: $x10 = COPY [[ADD]]
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; RV32IBT: PseudoRET implicit $x10
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; RV64I-LABEL: name: cmov_interleaved_bad
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; RV64I: successors: %bb.1, %bb.2
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; RV64I: liveins: $x10, $x11, $x12, $x13
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; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13
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; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
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; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
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; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
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; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
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; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
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; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2
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; RV64I: .1:
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; RV64I: .2:
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; RV64I: successors: %bb.3, %bb.4
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; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
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; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
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; RV64I: BNE [[ANDI]], [[COPY4]], %bb.4
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; RV64I: .3:
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; RV64I: .4:
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; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
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; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
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; RV64I: $x10 = COPY [[ADD]]
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; RV64I: PseudoRET implicit $x10
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; RV64IBT-LABEL: name: cmov_interleaved_bad
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; RV64IBT: successors: %bb.1, %bb.2
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; RV64IBT: liveins: $x10, $x11, $x12, $x13
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; RV64IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13
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; RV64IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
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; RV64IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
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; RV64IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
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; RV64IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
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; RV64IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
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; RV64IBT: BNE [[ANDI]], [[COPY4]], %bb.2
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; RV64IBT: .1:
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; RV64IBT: .2:
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; RV64IBT: successors: %bb.3, %bb.4
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; RV64IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
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; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
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; RV64IBT: BNE [[ANDI]], [[COPY4]], %bb.4
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; RV64IBT: .3:
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; RV64IBT: .4:
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; RV64IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
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; RV64IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
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; RV64IBT: $x10 = COPY [[ADD]]
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; RV64IBT: PseudoRET implicit $x10
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%3:gpr = COPY $x13
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%2:gpr = COPY $x12
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%1:gpr = COPY $x11
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%0:gpr = COPY $x10
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%5:gpr = ANDI %0, 1
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%6:gpr = COPY $x0
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%7:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %1, %2
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%8:gpr = ADDI %7, 1
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%9:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %3, %2
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%10:gpr = ADD %7, killed %9
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$x10 = COPY %10
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PseudoRET implicit $x10
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...
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---
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# Demonstrate that debug info associated with selects is correctly moved to
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# the tail basic block, while debug info associated with non-selects is left
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# in the head basic block.
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name: cmov_interleaved_debug_value
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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- { id: 6, class: gpr }
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- { id: 7, class: gpr }
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- { id: 8, class: gpr }
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- { id: 9, class: gpr }
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- { id: 10, class: gpr }
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liveins:
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- { reg: '$x10', virtual-reg: '%0' }
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- { reg: '$x11', virtual-reg: '%1' }
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- { reg: '$x12', virtual-reg: '%2' }
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- { reg: '$x13', virtual-reg: '%3' }
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body: |
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bb.0:
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liveins: $x10, $x11, $x12, $x13
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; RV32I-LABEL: name: cmov_interleaved_debug_value
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; RV32I: successors: %bb.1, %bb.2
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; RV32I: liveins: $x10, $x11, $x12, $x13
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; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x13
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; RV32I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
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; RV32I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
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; RV32I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
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; RV32I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
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; RV32I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
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; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
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; RV32I: DBG_VALUE [[ADDI]], $noreg
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; RV32I: BNE [[ANDI]], [[COPY4]], %bb.2
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; RV32I: .1:
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; RV32I: .2:
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; RV32I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
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; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
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; RV32I: DBG_VALUE [[PHI]], $noreg
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; RV32I: DBG_VALUE [[PHI1]], $noreg
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; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
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; RV32I: $x10 = COPY [[ADD]]
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; RV32I: PseudoRET implicit $x10
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; RV32IBT-LABEL: name: cmov_interleaved_debug_value
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; RV32IBT: successors: %bb.1, %bb.2
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; RV32IBT: liveins: $x10, $x11, $x12, $x13
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; RV32IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13
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; RV32IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
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; RV32IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
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; RV32IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
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; RV32IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
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; RV32IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
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; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
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; RV32IBT: DBG_VALUE [[ADDI]], $noreg
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; RV32IBT: BNE [[ANDI]], [[COPY4]], %bb.2
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; RV32IBT: .1:
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; RV32IBT: .2:
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; RV32IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
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; RV32IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
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; RV32IBT: DBG_VALUE [[PHI]], $noreg
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; RV32IBT: DBG_VALUE [[PHI1]], $noreg
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; RV32IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
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; RV32IBT: $x10 = COPY [[ADD]]
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; RV32IBT: PseudoRET implicit $x10
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; RV64I-LABEL: name: cmov_interleaved_debug_value
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; RV64I: successors: %bb.1, %bb.2
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; RV64I: liveins: $x10, $x11, $x12, $x13
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; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13
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; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
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; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
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; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
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; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
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; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
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; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
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; RV64I: DBG_VALUE [[ADDI]], $noreg
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; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2
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; RV64I: .1:
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; RV64I: .2:
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; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
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; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
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; RV64I: DBG_VALUE [[PHI]], $noreg
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; RV64I: DBG_VALUE [[PHI1]], $noreg
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; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
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; RV64I: $x10 = COPY [[ADD]]
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; RV64I: PseudoRET implicit $x10
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; RV64IBT-LABEL: name: cmov_interleaved_debug_value
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; RV64IBT: successors: %bb.1, %bb.2
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; RV64IBT: liveins: $x10, $x11, $x12, $x13
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; RV64IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13
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; RV64IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
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; RV64IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
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; RV64IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
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; RV64IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
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; RV64IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
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; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
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; RV64IBT: DBG_VALUE [[ADDI]], $noreg
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; RV64IBT: BNE [[ANDI]], [[COPY4]], %bb.2
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; RV64IBT: .1:
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; RV64IBT: .2:
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; RV64IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
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; RV64IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
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; RV64IBT: DBG_VALUE [[PHI]], $noreg
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; RV64IBT: DBG_VALUE [[PHI1]], $noreg
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; RV64IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
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; RV64IBT: $x10 = COPY [[ADD]]
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; RV64IBT: PseudoRET implicit $x10
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%3:gpr = COPY $x13
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%2:gpr = COPY $x12
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%1:gpr = COPY $x11
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%0:gpr = COPY $x10
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%5:gpr = ANDI %0, 1
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%6:gpr = COPY $x0
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%7:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %1, %2
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DBG_VALUE %7, $noreg
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%8:gpr = ADDI %0, 1
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DBG_VALUE %8, $noreg
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%9:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %3, %2
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DBG_VALUE %9, $noreg
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%10:gpr = ADD %7, killed %9
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$x10 = COPY %10
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PseudoRET implicit $x10
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...
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---
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