a33ce06cf5
The default promotion uses zero extends that become shifts. We cam use sign extend instead which is better for RISCV. I've used two different implementations based on whether we have minu/maxu instructions. Differential Revision: https://reviews.llvm.org/D98683
229 lines
6.2 KiB
LLVM
229 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb
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declare i4 @llvm.usub.sat.i4(i4, i4)
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declare i8 @llvm.usub.sat.i8(i8, i8)
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declare i16 @llvm.usub.sat.i16(i16, i16)
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declare i32 @llvm.usub.sat.i32(i32, i32)
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declare i64 @llvm.usub.sat.i64(i64, i64)
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define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
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; RV32I-LABEL: func:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a2, a0
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; RV32I-NEXT: sub a1, a0, a1
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: bltu a2, a1, .LBB0_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: .LBB0_2:
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: func:
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; RV64I: # %bb.0:
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; RV64I-NEXT: mv a2, a0
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; RV64I-NEXT: subw a1, a0, a1
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; RV64I-NEXT: mv a0, zero
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; RV64I-NEXT: bltu a2, a1, .LBB0_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: mv a0, a1
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; RV64I-NEXT: .LBB0_2:
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; RV64I-NEXT: ret
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;
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; RV32IZbb-LABEL: func:
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; RV32IZbb: # %bb.0:
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; RV32IZbb-NEXT: maxu a0, a0, a1
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; RV32IZbb-NEXT: sub a0, a0, a1
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; RV32IZbb-NEXT: ret
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;
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; RV64IZbb-LABEL: func:
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; RV64IZbb: # %bb.0:
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; RV64IZbb-NEXT: maxu a0, a0, a1
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; RV64IZbb-NEXT: subw a0, a0, a1
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; RV64IZbb-NEXT: ret
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%tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %y);
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ret i32 %tmp;
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}
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define i64 @func2(i64 %x, i64 %y) nounwind {
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; RV32I-LABEL: func2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a4, a0, a2
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; RV32I-NEXT: sub a3, a1, a3
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; RV32I-NEXT: sub a3, a3, a4
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; RV32I-NEXT: sub a2, a0, a2
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; RV32I-NEXT: beq a3, a1, .LBB1_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sltu a4, a1, a3
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; RV32I-NEXT: j .LBB1_3
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; RV32I-NEXT: .LBB1_2:
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; RV32I-NEXT: sltu a4, a0, a2
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; RV32I-NEXT: .LBB1_3:
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: bnez a4, .LBB1_5
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; RV32I-NEXT: # %bb.4:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: mv a1, a3
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; RV32I-NEXT: .LBB1_5:
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: func2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: mv a2, a0
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; RV64I-NEXT: sub a1, a0, a1
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; RV64I-NEXT: mv a0, zero
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; RV64I-NEXT: bltu a2, a1, .LBB1_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: mv a0, a1
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; RV64I-NEXT: .LBB1_2:
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; RV64I-NEXT: ret
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;
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; RV32IZbb-LABEL: func2:
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; RV32IZbb: # %bb.0:
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; RV32IZbb-NEXT: sltu a4, a0, a2
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; RV32IZbb-NEXT: sub a3, a1, a3
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; RV32IZbb-NEXT: sub a3, a3, a4
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; RV32IZbb-NEXT: sub a2, a0, a2
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; RV32IZbb-NEXT: beq a3, a1, .LBB1_2
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; RV32IZbb-NEXT: # %bb.1:
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; RV32IZbb-NEXT: sltu a4, a1, a3
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; RV32IZbb-NEXT: j .LBB1_3
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; RV32IZbb-NEXT: .LBB1_2:
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; RV32IZbb-NEXT: sltu a4, a0, a2
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; RV32IZbb-NEXT: .LBB1_3:
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; RV32IZbb-NEXT: mv a0, zero
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; RV32IZbb-NEXT: mv a1, zero
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; RV32IZbb-NEXT: bnez a4, .LBB1_5
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; RV32IZbb-NEXT: # %bb.4:
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; RV32IZbb-NEXT: mv a0, a2
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; RV32IZbb-NEXT: mv a1, a3
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; RV32IZbb-NEXT: .LBB1_5:
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; RV32IZbb-NEXT: ret
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;
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; RV64IZbb-LABEL: func2:
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; RV64IZbb: # %bb.0:
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; RV64IZbb-NEXT: maxu a0, a0, a1
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; RV64IZbb-NEXT: sub a0, a0, a1
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; RV64IZbb-NEXT: ret
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%tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %y);
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ret i64 %tmp;
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}
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define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
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; RV32I-LABEL: func16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a2, a0
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; RV32I-NEXT: sub a1, a0, a1
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: bltu a2, a1, .LBB2_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: .LBB2_2:
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: func16:
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; RV64I: # %bb.0:
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; RV64I-NEXT: mv a2, a0
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; RV64I-NEXT: sub a1, a0, a1
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; RV64I-NEXT: mv a0, zero
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; RV64I-NEXT: bltu a2, a1, .LBB2_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: mv a0, a1
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; RV64I-NEXT: .LBB2_2:
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; RV64I-NEXT: ret
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;
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; RV32IZbb-LABEL: func16:
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; RV32IZbb: # %bb.0:
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; RV32IZbb-NEXT: maxu a0, a0, a1
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; RV32IZbb-NEXT: sub a0, a0, a1
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; RV32IZbb-NEXT: ret
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;
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; RV64IZbb-LABEL: func16:
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; RV64IZbb: # %bb.0:
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; RV64IZbb-NEXT: maxu a0, a0, a1
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; RV64IZbb-NEXT: sub a0, a0, a1
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; RV64IZbb-NEXT: ret
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%tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y);
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ret i16 %tmp;
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}
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define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
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; RV32I-LABEL: func8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a2, a0
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; RV32I-NEXT: sub a1, a0, a1
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: bltu a2, a1, .LBB3_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: .LBB3_2:
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: func8:
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; RV64I: # %bb.0:
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; RV64I-NEXT: mv a2, a0
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; RV64I-NEXT: sub a1, a0, a1
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; RV64I-NEXT: mv a0, zero
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; RV64I-NEXT: bltu a2, a1, .LBB3_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: mv a0, a1
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; RV64I-NEXT: .LBB3_2:
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; RV64I-NEXT: ret
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;
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; RV32IZbb-LABEL: func8:
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; RV32IZbb: # %bb.0:
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; RV32IZbb-NEXT: maxu a0, a0, a1
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; RV32IZbb-NEXT: sub a0, a0, a1
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; RV32IZbb-NEXT: ret
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;
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; RV64IZbb-LABEL: func8:
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; RV64IZbb: # %bb.0:
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; RV64IZbb-NEXT: maxu a0, a0, a1
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; RV64IZbb-NEXT: sub a0, a0, a1
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; RV64IZbb-NEXT: ret
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%tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y);
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ret i8 %tmp;
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}
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define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
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; RV32I-LABEL: func3:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a2, a0
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; RV32I-NEXT: sub a1, a0, a1
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: bltu a2, a1, .LBB4_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: .LBB4_2:
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: func3:
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; RV64I: # %bb.0:
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; RV64I-NEXT: mv a2, a0
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; RV64I-NEXT: sub a1, a0, a1
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; RV64I-NEXT: mv a0, zero
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; RV64I-NEXT: bltu a2, a1, .LBB4_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: mv a0, a1
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; RV64I-NEXT: .LBB4_2:
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; RV64I-NEXT: ret
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;
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; RV32IZbb-LABEL: func3:
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; RV32IZbb: # %bb.0:
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; RV32IZbb-NEXT: maxu a0, a0, a1
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; RV32IZbb-NEXT: sub a0, a0, a1
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; RV32IZbb-NEXT: ret
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;
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; RV64IZbb-LABEL: func3:
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; RV64IZbb: # %bb.0:
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; RV64IZbb-NEXT: maxu a0, a0, a1
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; RV64IZbb-NEXT: sub a0, a0, a1
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; RV64IZbb-NEXT: ret
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%tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y);
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ret i4 %tmp;
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}
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